Device and method for detecting controller signal errors in flash memory

#This disclosure relates to systems and methods for detecting errors in control and data signals between a memory controller and a memory device.

#A memory device is usually controlled by a memory controller, which, by sending commands to the memory device, can control, for example, operations of the memory device, such as reading or writing of the memory device. The controller's commands and data may be sent to the memory device via a data bus including one or more input/output lines or communication paths connecting with an interface of the memory device. The interface may be configured for parallel or serial communications transmitted according to a particular protocol.

#Examples of a “read” and “write” protocol that may be used for serial communications are shown in the timing diagrams of FIGS. 1A and 1B. As shown in FIG. 1A, a controller may output a chip select signal 102 as a chip select output (CS#), a clock signal 104 as a clock output (CLK), and an access control signal 106 as one or more data input/outputs (DQ[7:0]). In the examples shown, a “low” chip select signal 102 enables serial access to the memory device for a command cycle, which extends for a duration of a plurality of clock pulses of the clock signal 104. The access control signal 106 for a read command, shown in FIG. 1A, includes a plurality of command (CMD) bits 110, which may include, for example, a 2-byte command signaling the memory device to start a read operation. Following the command bits, the access control signal includes a plurality of address bits 120, which may include, for example, a 4-byte address indicating a read address of the memory device. Next, the example read protocol includes a dummy cycle 125, as part of the access control signal 106, which may extend for a plurality of clock pulses, such as the four clock pulses shown, to wait for the memory device to prepare the data for output. After the dummy cycle 125, the access control signal 106 includes a plurality of read data bits 130. In the example shown, the controller may strobe the CMD bits 110 and the address bits 120 at rising edges of the clock signal 104, whereas the memory device may strobe the read data bits 130 at falling edges of the clock signal 104. The chip select signal 102 is then driven “high” to end the read command cycle.

#FIGS. 1A and 1B illustrate timing diagrams of conventional serial communication read and write protocols.

#FIG. 2 shows an exemplary memory system 200 of the disclosed embodiments.

#FIG. 3 is a flowchart showing a process according to an exemplary embodiment for controlling a memory device.

#Embodiments consistent with the disclosure include systems, devices and methods for detecting transmission errors over a data bus in a memory system. The disclosed embodiments are directed to a serial communications protocol providing an error detection signal used to verify the correctness of information provided in an access control signal transferred between a controller and a memory device. In some embodiments, an exemplary error detection signal is transferred using the same data bus line or lines used for transferring access control signal information between the controller and memory device. In other embodiments, an exemplary error detection signal is transferred using a dedicated line between dedicated pins respectively associated with the controller and memory device. In the disclosed embodiments, an error detection signal includes information corresponding to one or more of command, address or data information included in the access control signal.

#Hereinafter, embodiments consistent with the disclosure will be described with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

#FIG. 2 schematically illustrates an exemplary memory system 200 according to the disclosed embodiments. Memory system 200 includes a memory controller 210 and a memory device 220. Memory controller 210 and memory device 220 each include an interface with a plurality of corresponding pins for receiving and transferring communication signals between each other. As shown, a first set of pins (212, 222) corresponds to clock output/input pins (CLK) for communicating a system clock signal for synchronizing signal communications between memory controller 210 and memory device 220. A second set of pins (214,224) corresponds to chip select (also known as slave select) output/input pins (CS#) for activating or enabling memory device 220 to communicate with memory controller 210. A third set of pins (216, 226) corresponds to data bus pins (DQ[7:0]) for transferring and receiving an access control signal to and from memory device 220. In some embodiments, a data bus coupled between pin sets 216 and 226 is configured to include a 1, 2 or 4 pin/line bus. The data bus may be configured to both transfer and receive control signals to and from memory device 220 using common pins or wires. Alternatively, the data bus may include distinct pins or wires separating signal input communications and output communications.