Test mode circuit for memory apparatus
AssigneeMicron Technology, Inc.
InventorToru Ishikawa
Life of this patent
Estimating the term…
Abstract
Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number.
Claims19
An apparatus comprising:
- at least one memory cell array comprising a plurality of memory cells;
- and
- a control circuit configured to receive read data from the plurality of memory cells, configured to compare the read data with reference data, and further configured to provide an error signal,
- wherein the control circuit is further configured to provide the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and
- wherein the control circuit is further configured to suppress providing the error signal when the number of bit errors detected is less than the predetermined number,
- wherein the control circuit comprises,
- a first comparison circuit configured to receive the reference data, configured to provide first intermediate error signals;
- and
- a second comparison circuit configured to receive the first intermediate error signals, and further configured to provide a second error signal when a number of bit errors is greater than the predetermined number.
An apparatus comprising:
- a first chip including a plurality of memory cells and a control circuit configured to receive read data from the plurality of memory cells, to compare the read data with expectation data, to output an error signal when detects N bit errors and not to output the error signal when detects N−1 bit error(s), N being an integer greater than or equal to two;
- and
- a second chip coupled to the first chip to receive the read data, the second chip including an error correction circuit configured to correct the N−1 bit error(s) of the read data,
- wherein the first chip comprises at least one memory cell array comprising the plurality of memory cells, the at least one memory cell array coupled to the error correction circuit and the control circuit,
- wherein the memory cell array is configured to receive data and syndromes from the error correction circuit, configured to store the data and syndromes in the plurality of memory cells, configured to read the stored data and syndromes from the plurality of memory cells, and further configured to provide the data and syndromes to the control circuit.
A control circuit coupled to a plurality of memory cells, the control circuit comprising:
- a register configured to provide a reference data;
- a first comparison circuit configured to receive the reference data, configured to provide first intermediate error signals, and
- a second comparison circuit configured to receive the first intermediate error signals, and further configured to provide a second error signal when a number of bit errors detected is greater than or equal to a predetermined number,
- wherein the control circuit is configured to receive read data from the plurality of memory cells, configured to compare the read data with the reference data, and further configured to provide an error signal,
- wherein the control circuit is further configured to provide the error signal when the number of bit errors detected is greater than or equal to the predetermined number, and
- wherein the control circuit is further configured to suppress providing the error signal when the number of bit errors detected is less than the predetermined number.
Dependencies are inferred from the claim text.