Memory testing circuit and testing method using same

A memory testing circuit for testing a memory having an analog voltage I/O terminal, comprising:

• a VPPIO I/O module having an encoder circuit, an analog terminal, a first digital input terminal and a first digital output terminal, the analog terminal coupled to the analog voltage I/O terminal of the memory, the VPPIO I/O module coupled to a single signal pin of a test instrument for receiving a stimulating input therefrom, the stimulating input including an analog signal or a digital signal, the VPPIO I/O module configured to transmit the analog signal in the stimulating input from the single signal pin to the analog voltage I/O terminal of the memory or to encode the digital signal in the stimulating input using the encoder circuit;
• a self-test circuit coupled to the memory and having a decoder circuit, a clock terminal, a second digital input terminal and a second digital output terminal, the second digital input terminal and the second digital output terminal coupled to the first digital input terminal and the first digital output terminal of the VPPIO I/O module, respectively, the self-test circuit configured to receive an encoded digital signal from the VPPIO I/O module, decode the encoded digital signal into a parallel signal using the decoder circuit and output the parallel signal to the memory;
• and
• an on-chip clock circuit coupled to the clock terminal of the self-test circuit and configured to provide a clock signal to the self-test circuit,
• wherein the VPPIO I/O module, the self-test circuit and the on-chip clock circuit are independent from one another;
• and
• wherein the self-test circuit and the VPPIO I/O module are further configured to receive a feedback signal from the memory and determine whether the feedback signal is consistent with an expected signal or not, thereby accomplishing testing of the memory.