Write enhancement for one time programmable (OTP) semiconductors

In an array of one-time programmable (OTP) memory cells, each memory cell having a MOSFET pass transistor with a gate electrode over a channel region between two source/drain regions, and a MOSFET programming element with a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor, the other source/drain region of the MOSFET pass transistor coupled to a bit line, a method of programming the memory cell comprising applying a first programming pulse by:

• setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor;
• setting a second voltage of the first polarity on the gate electrode of the programming element;
• setting a third voltage of a second polarity on the bit line;
• whereby a voltage across an oxide layer between the gate electrode and channel region of the programming element is created to rupture the oxide layer and program the programming element;
• and
• applying a second programming pulse including a negative voltage.

A semiconductor device comprising:

• an array of one-time programmable (OTP) memory cells, each memory cell having
• a MOSFET pass transistor having two source/drain regions, and a gate electrode over a channel region between the two source/drain regions;
• a MOSFET programming element having two source/drain regions and a gate electrode over a channel region between the two source/drain regions, one of the source/drain regions either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor;
• a first word line connected to the gate of the MOSFET pass transistor;
• a second word line connected to the gate electrode of the MOSFET programming element;
• a bit line connected to the source/drain region of the MOSFET pass transistor not part of, nor connected to, a source/drain region of the MOSFET programming element;
• and
• a negative voltage source coupled to the bit line during a first programming pulse during programming of the memory cell, and again coupled to the bit line during a second programming pulse.