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AssigneeSanDisk Technologies LLC
InventorsMurong Lang, Deepanshu Dutta, Cynthia Hsu
Estimating the term…
Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.
An apparatus, comprising:
A method, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.
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Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
Auxiliary circuits: writing or programming circuits or methods
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
About 9 years 4 months of term left · ends 7 Mar 2036 (estimated)
The present technology relates to operation of memory devices.
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
However, various challenges are presented in operating such memory devices.
FIG. 1 is a block diagram of an example memory device.
FIG. 2 depicts blocks of memory cells in an example two-dimensional configuration of the memory structure 126 of FIG. 1.
FIG. 3 is a perspective view of a memory device 600 comprising a set of blocks in an example three-dimensional configuration of the memory structure 126 of FIG. 1.
Techniques are provided for optimizing the programming of a memory device. A corresponding memory device is also provided.
In some memory devices, a charge-storing material such as a floating gate or a charge-trapping material is used to store a charge which represents a data state. A charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers. Other types of memory structures include resistance-switching memories such as ReRAM cross-point memories, magnetoresistive memory (e.g., MRAM and STT-RAM), and phase change memory (e.g., PCRAM).
A memory device can include memory cells which are arranged in strings, for instance, where select gate transistors are provided at the ends of the string to selectively connect a channel of the string to a source line or bit line.