Nonvolatile memory devices and methods of operating the same

A nonvolatile memory device, comprising:

• a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of cell strings formed vertically on a substrate, the plurality of cell strings coupled to a plurality of bit-lines, the plurality of cell strings each including memory cells connected to a string selection transistor and ground selection transistor;
• a voltage generator configured to generate word-line voltages in response to control signals;
• an address decoder configured to apply the word-line voltages to the memory cell array in response an address signal;
• a page buffer circuit coupled to the memory cell array through the plurality of bit-lines;
• and
• a control circuit, wherein
• the control circuit is configured to control the voltage generator and the page buffer circuit,
• the control circuit is configured to perform an erase operation and an erase verification operation on a first memory block of the memory blocks in response to an erase command, and
• the control circuit is configured control the voltage generator and the page buffer circuit such that the voltage generator and the page buffer circuit perform a first sensing operation on the string selection transistor of each of the plurality of cell strings coupled to at least some bit-lines of the first memory block,
• the first sensing operation is based on a first sensing scheme selected among a plurality of sensing schemes,
• the control circuit is configured perform selectively a second sensing operation on the ground selection transistor of each of the plurality of cell strings coupled to at least some bit-lines of the first memory block based on a result of the first sensing operation, and
• the second sensing operation being based on a second sensing scheme selected among the plurality of sensing schemes.

A method of operating a nonvolatile memory device including a plurality of memory blocks on a substrate, each of the memory blocks including a plurality of cell strings coupled to a plurality of bit lines, each of the plurality of cell strings including a plurality of memory cells connected to each other between a string selection transistor and a ground selection transistor on the substrate, the method comprising:

• performing an erase operation on a first memory block of the plurality of memory blocks;
• performing an erase verification operation on the first memory block;
• performing a first sensing operation on the string selection transistors of at least two cell strings of among the plurality of cell strings of the first memory block,
• the first sensing operation including determining whether at least one of the string selection transistors of the at least two cell strings of the first memory block are in an off state or an on state using a first sensing scheme selected among a plurality of sensing schemes;
• and
• determining whether the first memory block is a fail block using a result of the first sensing operation.