Methods for programming and accessing DDR compatible resistive change element arrays

A method of programming the informational state of a resistive change element, said method comprising:

• providing a resistive change element, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first informational state and a second resistance value corresponding to a second informational state;
• receiving data input pulses from an external data bus to a data I/O buffer/driver circuit at an input data rate and system level logic voltage amplitudes, wherein said I/O buffer driver circuit converts said input pulses into programming pulses and provides said programming pulses to an on-chip data bus, said programming pulses having at a data rate of no more than half said input data rate and programming level voltage amplitudes;
• wherein said on-chip data bus provides said programming data pulses to sense amplifiers via bi-directional data bus control circuits, each of said sense amplifiers transmitting programming pulses to at least one bit line electrically coupled to said resistive change element by a cell select device;
• wherein a programming voltage pulse having a programming voltage level corresponding to a first informational state is stored within said resistive change element and a programming voltage pulse having a programming level corresponding to a second informational state is stored within said resistive change element.

A method of programming the informational state of a resistive change element, said method comprising:

• providing a resistive change element, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first informational state and a second resistance value corresponding to a second informational state;
• receiving data input pulses from an external data bus to a data I/O buffer/driver circuit at an input data rate and logic operation voltage amplitudes, wherein said I/O buffer driver circuit converts said input pulses into programming pulses and provides said programming pulses to an on-chip data bus, said programming pulses having at a data rate of no more than half said input data rate and logic operation voltage amplitudes;
• wherein said on-chip data bus provides said programming data pulses to sense amplifiers via bi-directional data bus control circuits, each of said sense amplifiers transmitting programming pulses to at least one input terminal of a voltage shifting element having at least one output coupled through a select circuit to at least one bit line electrically coupled to said resistive change element by a cell select device;
• wherein a programming voltage pulse having a programming voltage level corresponding to a first informational state is stored within said resistive change element and a programming voltage pulse having a programming level corresponding to a second informational state is stored within said resistive change element.