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US 9,852,792 B2Granted
Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency
AssigneeHewlett Packard Enterprise Development LP
InventorsNaveen Muralimanohar, Han Bin Yoon, Norman Paul Jouppi
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Abstract
A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.
Claims7
A non-volatile multi-level cell (“MLC”) memory device, comprising:
- an array of non-volatile memory cells, each non-volatile memory cell to store multiple groups of bits, each group of bits among the multiple groups being mapped to logically separate memory addresses;
- a row buffer having multiple buffer portions, each buffer portion to store one or more bits from the memory cells and having different read and write latencies and energies;
- and
- a memory controller to issue write requests to different bits in a set of non-volatile memory cells in the array of non-volatile memory cells and instruct the memory device to coalesce the write requests to make a single write to the set of non-volatile memory cells.
1 more element
Dependencies are inferred from the claim text.