Semiconductor memory device, chip ID generation method thereof and manufacturing method thereof

A chip identity (ID) generation method for a semiconductor memory device including a plurality of programmable resistance memory cells, the chip ID generation method including:

• applying a forming pulse to a first group and a second group of the plurality of programmable resistance memory cells, for inducing a change in resistance in the first group of the programmable resistance memory cells from an initial resistance range to an intermediate resistance range, while the second group of the programmable resistance memory cells has a resistance outside the intermediate resistance range;
• determining a forming rate according to the first group of the programmable resistance memory cells;
• when the forming rate is lower than a first forming threshold rate, adjusting the forming pulse until the forming rate is higher than the first forming threshold rate;
• when the forming rate is higher than the first forming threshold rate but lower than the second forming threshold rate, adjusting the forming pulse until the forming rate is higher than the second forming threshold rate;
• applying a programming pulse to the first and second groups of the programmable resistance memory cells, for inducing a change in resistance of the first group from the intermediate resistance range to a first final resistance range, while the second group of the programmable resistance memory cells has a resistance in a second final resistance range that does not overlap the first final resistance range;
• and
• generating the chip ID of the semiconductor memory device based on the first and second groups of the programmable memory cells.

A manufacturing method for a semiconductor memory device, the manufacturing method including:

• forming a plurality of programmable resistance memory cells on the semiconductor memory device;
• connecting the semiconductor memory device to a system configured to apply a physical unclonable function to the programmable resistance memory cells of the semiconductor memory device;
• and
• using the system to generate a chip identity (ID) from the programmable resistance memory cells by:
• applying a forming pulse to a first group and a second group of the plurality of programmable resistance memory cells, for inducing a change in resistance in the first group of the programmable resistance memory cells from an initial resistance range to an intermediate resistance range, while the second group of the programmable resistance memory cells has a resistance outside the intermediate resistance range;
• determining a forming rate according to the first group of the programmable resistance memory cells;
• when the forming rate is lower than a first forming threshold rate, adjusting the forming pulse until the forming rate is higher than the first forming threshold rate;
• when the forming rate is higher than the first forming threshold rate but lower than the second forming threshold rate, adjusting the forming pulse until the forming rate is higher than the second forming threshold rate;
• applying a programming pulse to the first and second groups of the programmable resistance memory cells, for inducing a change in resistance of the first group from the intermediate resistance range to a first final resistance range, while the second group of the programmable resistance memory cells has a resistance in a second final resistance range that does not overlap the first final resistance range;
• and
• generating the chip ID of the semiconductor memory device based on the first and second groups of the programmable memory cells.