US 9,852,788 B2Granted

Multipage program scheme for flash memory

AssigneeConversant Intellectual Property Management Inc.

InventorJin-Ki Kim

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Abstract

A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The selected wordline connected to the cells to be programmed is driven with predetermined program profiles at different time intervals, where each predetermined program profile is configured for shifting an erase threshold voltage to a specific threshold voltage corresponding to a specific logic state. A multi-page bitline controller biases each bitline to enable or inhibit programming during each of the time intervals, in response to the combination of specific logic states of the bits belonging to each page of data that are associated with that respective bitline.

Claims13

Dependent claims

A NAND flash memory device comprising:

a plurality of I/O ports configured to receive a single multi-page program request from a memory controller, the single multi-page program request comprising at least two iterative command and data input sequences, each command and data input sequence comprising command data, address data and write data;
a ready/busy port configured to output a ready/busy signal indicating a busy status of the NAND flash memory device, the ready/busy signal indicates a busy status in between the at least two iterative command and data input sequences;
a flash memory array comprising NAND type memory cells connected to wordlines and coupled to bitlines, each wordline corresponding to a single physical page comprising M logical pages, M being an integer greater than 1;
bitline access circuitry configured to store M logical pages of data before execution of a single multi-page programming cycle, and bias the bitlines to one of enable and inhibit programming for each of 2M−1 programming iterations based on a combination of bits corresponding to each bitline from the M logical pages of data during execution of the single multi-page programming cycle, each logical page of data being provided from the write data;
and
row circuits configured to drive a selected wordline with different time periods for each of the 2M−1 programming iterations while the bitlines are biased to enable or inhibit programming based on a combination of logic states of the M logical pages of data, and program the M logical pages of data to a single physical page of memory cells in the single multi-page programming cycle.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/266,196Filed 15 Sep 2016 · continuation
Priority: 21 Jul 2010
Published: US 2017/0004877 A15 Jan 2017
Granted: 26 Dec 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C
Static stores

Family

Application61/366,375Us provisional application · filed 21 Jul 2010
Application13/186,789Parent of this continuation · filed 20 Jul 2011
US 2017/0004877 A1Pre-grant publication · published 5 Jan 2017
US 9,484,097 B2Parent of this continuation
US 2012/0020155 A1Published application
US 9,852,788 B2This patent

From the US filing history. Foreign family members aren’t listed.