Bit line clamp voltage generator for STT MRAM sensing
AssigneeInternational Business Machines Corporation
InventorJohn K. DeBrosse
Life of this patent
Estimating the term…
Abstract
A bit line clamp voltage generator circuit for a Spin Torque Transfer Magnetoresistive Random Access Memory is provided. The circuit includes a negative channel Field Effects Transistor having a source, a drain, and a gate, the gate being connected to the drain. The circuit further includes a resistor Rs having a first end connected to a first voltage and a second end connected to the source. The circuit also includes a resistor Rd having a first end connected to a second voltage and a second end connected to the drain to form an output node for outputting a bit line clamp voltage.
Claims12
A bit line clamp voltage generator circuit for a Spin Torque Transfer Magnetoresistive Random Access Memory, the circuit comprising:
- a transistor having a source, a drain, and a gate, the gate being connected to the drain;
- a resistor Rs having a first end connected to a first voltage and a second end connected to the source;
- and
- a resistor Rd having a first end connected to a second voltage and a second end connected to the drain to form an output node for outputting a bit line clamp voltage;
- and
- a first switching transistor for selectively disconnecting the resistor Rd from the second voltage in a circuit disable mode;
- and
- a second switching transistor for selectively pulling down the output node in the circuit disable mode.
A method for generating a bit line clamp voltage for a Spin Torque Transfer Magnetoresistive Random Access Memory, the method comprising:
- providing a transistor having a source, a drain, and a gate, the gate being connected to the drain;
- providing a resistor Rs having a first end connected to a first voltage and a second end connected to the source;
- providing a resistor Rd having a first end connected to a second voltage and a second end connected to the drain to form an output node for outputting a bit line clamp voltage;
- providing a first switching transistor to selectively disconnect the resistor Rd from the second voltage in a circuit disable mode;
- and
- providing a second switching transistor to selectively pull down the output node in the circuit disable mode,
- wherein the bit line clamp voltage is output from the output node responsive to application of the first voltage and the second voltage.
Dependencies are inferred from the claim text.