Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages

A sense amplifier, comprising:

• a latching means, comprising:
• a means for receiving a data input voltage;
• and
• a means for receiving a reference input voltage;
• a means for generating an amplified data output voltage on an output node and an amplified complement output voltage on a complement output node based on a differential voltage based on the data input voltage and the reference input voltage, in response to a sense amplifier phase signal;
• a means for storing the data input voltage from a sensing circuit;
• a means for storing the reference input voltage from the sensing circuit;
• an input means coupled to the means for storing the data input voltage, the input means for coupling the means for receiving the data input voltage to a reference node based on the data input voltage stored in the means for storing the data input voltage;
• a complement input means coupled to the means for storing the reference input voltage, the complement input means for comprising a gate coupled to the reference sense amplifier capacitor circuit, the complement input means for coupling the means for receiving the reference input voltage to the reference node based on the reference input voltage stored in the means for storing the reference input voltage;
• a means for discharging coupled to the input means and the complement input means, for discharging the input means and discharging the complement input means to cancel offset voltages of the input means and the complement input means, in response to a discharge phase signal;
• a data input means coupled to the means for storing the data input voltage, for passing the data input voltage directly to the means for storing the data input voltage in response to a voltage capture phase signal;
• and
• a reference input means coupled to the means for storing the reference input voltage, for passing the reference input voltage directly to the means for storing the reference input voltage in response to the voltage capture phase signal.

A method of sensing a differential voltage of a data input voltage and a reference input voltage, comprising:

• discharging a gate of an input transistor to an input threshold voltage of the input transistor and a gate of a complement input transistor to a complement input threshold voltage of the complement input transistor, to cancel offset voltages of the input transistor and the complement input transistor, in response to a discharge phase signal;
• storing a received data input voltage directly in a data sense amplifier capacitor coupled to the gate of the input transistor and in a reference sense amplifier capacitor coupled to the gate of the complement input transistor;
• adjusting both a voltage at the gate of the input transistor and the gate of the complement input transistor to the input threshold voltage plus the data input voltage, in response to a first voltage capture phase signal;
• pre-charging an output node and a complement output node of a latch circuit to a supply voltage at a supply node, in response to the first voltage capture phase signal;
• storing a received reference input voltage directly in the reference sense amplifier capacitor, in response to a second voltage capture phase signal;
• adjusting the voltage at the gate of the complement input transistor to the input threshold voltage plus the reference input voltage, in response to the second voltage capture phase signal;
• and
• generating an amplified data output voltage on an output node and an amplified complement output voltage on a complement output node based on a differential voltage based on the data input voltage and the reference input voltage.

A resistive memory sensing system, comprising:

• a memory array comprising a plurality of resistive memory bitcells each comprising a data resistive memory element and a reference resistive memory element, a storage state of each of the plurality of resistive memory bitcells based on a differential resistance between the data resistive memory element and the reference resistive memory element;
• a sensing circuit coupled to the memory array, the sensing circuit configured to:
• select a resistive memory bitcell among the plurality of resistive memory bitcells in response to a read operation;
• generate a data input voltage based on a resistance of the data resistive memory element of the selected resistive memory bitcell;
• and
• generate a reference input voltage based on a resistance of the reference resistive memory element of the selected resistive memory bitcell;
• and
• a sense amplifier configured to:
• discharge a gate of an input transistor to an input threshold voltage of the input transistor and a gate of a complement input transistor to a complement input threshold voltage of the complement input transistor, to cancel offset voltages of the input transistor and the complement input transistor, in response to a discharge phase signal;
• store the data input voltage from the sensing circuit directly in a data sense amplifier capacitor coupled to the gate of the input transistor and in a reference sense amplifier capacitor coupled to the gate of the complement input transistor;
• adjust both a voltage at the gate of the input transistor and the gate of the complement input transistor to the input threshold voltage plus the data input voltage, in response to a voltage capture phase signal;
• pre-charge an output node and a complement output node of a latch circuit to a supply voltage at a supply node, in response to a first voltage capture phase signal;
• store the reference input voltage received from the sensing circuit directly in the reference sense amplifier capacitor, in response to a second voltage capture phase signal;
• adjust the voltage at the gate of the complement input transistor to the input threshold voltage plus the reference input voltage, in response to the second voltage capture phase signal;
• and
• generate an amplified data output voltage on the output node and an amplified complement output voltage on the complement output node based on a differential voltage based on the data input voltage and the reference input voltage.