Dynamically allocable regions in non-volatile memories
AssigneeSTMicroelectronics S.r.l.
InventorsEmanuele Confalonieri, Giuseppe Russo, Luca Porzio
Life of this patent
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Abstract
An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the matrix into a plurality of subspaces; each subspace comprises at least one respective memory cell. The memory device further comprises selection means for selecting a subspace, operative means for performing an operation on all the memory cells of the selected subspace, and means for dynamically modifying the number of subspaces and/or the number of memory cells included in each subspace.
Claims28
A non-volatile memory device, said memory device including:
- a matrix of memory cells, each memory cell being individually programmable to at least one first logic level and individually erasable to a second logic level;
- a partition circuit for logically subdividing the matrix into a plurality of subspaces, each subspace comprising at least one respective memory cell;
- a selection circuit for selecting a subspace;
- an operative circuit for performing an operation on all the memory cells of the selected subspace, the operation including a verify operation, said verify operation being adapted to verify whether all the memory cells of the selected subspace are to a same selected logic value;
- and
- a circuit for dynamically modifying the number of memory cells included in each subspace.
A method, comprising:
- operating a non-volatile memory device comprising a matrix of memory cells, each memory cell being individually programmable to at least one first logic level and individually erasable to a second logic level;
- logically subdividing the matrix into a plurality of subspaces, each subspace comprising at least one respective memory cell;
- selecting a subspace;
- performing an operation on all the memory cells of the selected subspace;
- dynamically modifying the number of memory cells included in each subspace;
- and
- wherein said operation comprises verifying whether all the memory cells of the selected subspace are to a same selected logic level.
A memory, comprising:
- an array of non-volatile memory cells;
- a first circuit configured to dynamically partition the array into a first set of groups of memory cells, the partition corresponding to an address range, each group including at least one memory cell;
- and
- the first circuit further configured to verify a programming state of each memory cell in the first group of memory cells.
A system, comprising:
- a first integrated circuit, comprising:
- an array of non-volatile memory cells;
- a first circuit configured to dynamically partition the array into groups of memory cells, the partition corresponding to an address range, each group including at least one memory cell;
- the first circuit further configured to verify a programming state of each memory cell in the first group of memory cells;
- and
- a second integrated circuit coupled to the first integrated circuit.
Dependencies are inferred from the claim text.