Dual-port DDR4-DIMMs of SDRAM and NVRAM for SSD-blades and multi-CPU servers
AssigneeFuturewei Technologies, Inc.
InventorXiaobing Lee
Life of this patent
Estimating the term…
Abstract
A memory system is disclosed that includes a first FPGA controller coupled to a first SSD cluster, a first DDR4 DIMM and a second DDR4 DIMM. A second FPGA controller is coupled to a second SSD cluster, the first DDR4 DIMM and the second DDR4 DIMM, where the first and second FPGAs are operable to share access to the first and second DDR4 DIMMs and provide connectivity to a plurality of network resources. The dual-port design enables the use of existing SDRAM, MRAM and RRAM chips at low speed rates to reach DDR4 2.0 speed DIMM devices. The dual-port DDR4 DIMM comprises 1-to-2 data buffer splitters and a DDR3 or DDR2 to DDR4 bus adaptation/termination/relaying circuits to increase (e.g., double or quadruple) the chip speed of SDRAM, MRAM, and RRAM chips.
Claims19
A memory system, comprising:
- a first FPGA controller coupled to a first SSD cluster, a first DDR4 DIMM and a second DDR4 DIMM;
- a second FPGA controller coupled to a second SSD cluster, the first DDR4 DIMM and the second DDR4 DIMM, wherein the first and second FPGAs are operable to share access to the first and second DDR4 DIMMs and provide connectivity to a plurality of network resources;
- and
- a first network host attached to the first FPGA controller and a second network host attached to the second FPGA controller, wherein the first and second FPGA controllers provide a DMA-master interface and virtualized slave memory for the attached network hosts.
A memory system, comprising:
- a first FPGA controller coupled to a first SSD cluster, a first DDR4 DIMM and a second DDR4 DIMM;
- a second FPGA controller coupled to a second SSD cluster, the first DDR4 DIMM and the second DDR4 DIMM, wherein the first and second FPGAs are operable to share access to the first and second DDR4 DIMMs and provide connectivity to a plurality of network resources;
- and
- a command bus coupled to the first and second FPGA controller, wherein the command bus is operable to quarantine and reboot the first and second FPGA during failure.
A DDR4 dual-port DIMM, comprising:
- a controller operable to receive commands from a first and second FPGA controller;
- a first network device coupled to the first FPGA controller and a second network device coupled to the second FPGA controller;
- and
- a plurality of memory chips disposed on the dual-port DIMM, wherein pairs of the plurality of memory chips are connected to 1-to-2 data buffer splitters, even bytes of the DIMM are routed to the first FPGA, and odd bytes of the DIMM are routed to the second FPGA.
A DDR4 dual-port DIMM, comprising:
- a controller operable to receive commands from a first and second FPGA controller;
- a plurality of first memory chips disposed on a front side of the dual-port DIMM, wherein pairs of the plurality of first memory chips are connected to 1-to-2 data buffer splitters and controlled by the controller;
- and
- a plurality of second memory chips disposed on a back side of the dual-port DIMM, wherein groups of four of the plurality of second memory chips are connected to pairs of the 1-to-2 data buffer splitters and controlled by the controller, the effective speed of the first memory chips is doubled, and the effective speed of the second memory chips is quadrupled.
Dependencies are inferred from the claim text.