Method and system for designing a semiconductor chip based on grouping of hierarchial pins that permit communication between internal components of the semiconductor chip

#Embodiments of the present disclosure relate to circuit design, and in particular to circuit design based on a grouping of hierarchical pins that permit communication between internal components and partitions of a chip.

#Designing a complex semiconductor chip (referred to herein generally as “chip”) is usually a time consuming process, and requires several iterations. For example, a chip usually has thousands of internal pins for communication between various internal components and partitions of the chip. During a first iteration of the design of the chip, the pins, for example, are designed to be placed at specific locations in the chip. However, subsequent modification in the design of the chip typically necessitates a re-design in the placement of the pins. Such iterations in the design of the chip are labor intensive and time consuming.

#In various embodiments, the present disclosure provides a computer implemented method comprising: while designing a chip, identifying a plurality of partitions in the chip, for a first partition of the plurality of partitions in the chip, identifying a plurality of pins configured to interconnect the first partition with one or more other partitions of the plurality of partitions of the chip, assigning a name to each of the plurality of pins associated with the first partition of the plurality of partitions, based on the names assigned to each of the plurality of pins, forming a plurality of groups such that each group of the plurality of groups is associated with a corresponding one or more pins of the plurality of pins, and based on forming the plurality of groups, designing a first subset of the plurality of pins to be located at close proximity in the chip.

#Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Various embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

#FIG. 1 schematically illustrates a semiconductor chip divided in a plurality of partitions.

#FIG. 2 illustrates an example formation of a group of pins (referred to herein as “pin groups”) from a plurality of pins, while designing the semiconductor chip of FIG. 1.

#FIG. 1 schematically illustrates a semiconductor chip 100 (henceforth referred to as “chip 100”). The chip 100, for example, comprises a system on a chip (SOC). In an embodiment, the chip 100 is partitioned in a plurality of partitions 104a, . . . , 104h. Although FIG. 1 illustrates a specific number, specific shapes and specific sizes of the partitions, the chip 100 can have any different number, shapes and/or sizes of the partitions.

#In an embodiment, the partitions 104a, . . . , 104h partitions or divides the chip 100 in different functional or logical areas. Merely as an example, the partition 104a represents a processing core of the chip 104a, the partition 104b represents a level 1 (L1) cache of the chip, and so on.

#In an embodiment, a partition of the chip 100 communicates with one or more other partitions of the chip 100 via a corresponding plurality of pins. Three example pins 108 are illustrated in FIG. 1, which facilitate communication between the partition 104a and the partition 104d. Although only three example pins are illustrated in FIG. 1, the chip 100 can comprise hundreds, and even thousands of such pins. The pins are used for intra-partition communication, e.g., communication between two partitions of the chip 100. A pin is, for example, a connector that communicates signals between two corresponding partitions.