Automated layout for integrated circuits with nonstandard cells

A machine-readable storage medium with an executable program stored thereon, wherein the executable program contains instructions for one or more processors to perform the following:

• partition a circuit into one or more cells based on a circuit description;
• check availability of a layout of a cell of the one or more cells;
• generate the layout of the cell when there is no layout available for the cell, wherein the layout is generated by an automatic tool, and packaged in a form of a standard cell compatible with a standard cell placement and routing tool;
• and
• exporting the generated layout of the cell to the standard cell placement and routing tool;
• group transistors of the cell into one or more trails, wherein transistors in a trail can share diffusion area for a source and a drain of transistors;
• assign physical dimensions to transistors of a trail to become a stack of transistors;
• place the stack of transistors in a layout area with shared diffusion areas, and
• perform a local routing of the transistors of the cell.

A circuit design system, comprising:

• a storage medium;
• a processor;
• and
• program instructions stored in the data storage and executable by the processor to carry out functions including:
• partitioning a circuit into one or more cells based on a circuit description;
• checking availability of a layout of a cell of the one or more cells;
• using the available layout of the cell in a standard cell placement and routing tool;
• generating the layout of the cell when there is no layout available for the cell, wherein the layout is generated by an automatic tool, and packaged in a form of a standard cell compatible with the standard cell placement and routing tool;
• and
• exporting the generated layout of the cell to the standard cell placement and routing tool;
• grouping transistors of the cell into one or more trails, wherein transistors in a trail can share diffusion area for a source and a drain of transistors;
• assigning physical dimensions to transistors of a trail to become a stack of transistors;
• placing the stack of transistors in a layout area with shared diffusion areas, and
• performing a local routing of the transistors of the cell.