Standard cell library and methods of using the same

A method of operating a computing device for designing an integrated circuit (IC) using a standard cell library comprising information regarding a plurality of standard cells,

• the method comprising:
• receiving input data at the computing device defining the IC comprising at least one of the plurality of standard cells, the at least one of the plurality of standard cells comprising a pin which comprises first and second regions perpendicular to a stack direction;
• accessing a non-transitory computer readable storage medium storing the standard cell library that is coupled to the computing device, the standard cell library further comprising marker information corresponding to the second region of the pin;
• and
• placing and routing, by a processor of the computing device, the at least one of the plurality of standard cells included in the IC by disposing a via in the second region of the pin rather than the first region of the pin based on the marker information,
• wherein, if the via is disposed in the second region of the pin, a resistance value of the via is smaller than if the via is placed in the first region of the pin, and
• wherein the placing and routing the at least one of the plurality of standard cells comprises analyzing a timing characteristic of the IC based on the resistance value of the via disposed in the second region.

A method of operating a computing device using for designing an integrated circuit (IC) a standard cell library comprising information regarding a plurality of standard cells, the method comprising:

• receiving input data at the computing device defining the IC comprising at least one of the plurality of standard cells, the at least one of the plurality of standard cell comprising a pin which comprises first and second regions perpendicular to a stack direction;
• accessing a non-transitory computer readable storage medium storing the standard cell library that is coupled to the computing device, the standard cell library further comprising marker information corresponding to the second region of the pin;
• and
• placing and routing, by a processor of the computing device, the at least one of the plurality of standard cells included in the IC by disposing a via in the second region of the pin rather than the first region of the pin based on the marker information,
• wherein, if the via is disposed in the second region of the pin, a resistance value of the via is smaller than if the via is placed in the first region of the pin, and
• wherein the placing and routing the at least one of the plurality of standard cells comprises selecting a first standard cell connected to a critical path of the IC for disposing the via in the second region rather than other standard cells included in the IC not connected to the critical path of the IC.