Memory optimization in VLSI design using generic memory models
AssigneeeSilicon Corporation
InventorsPrasad Subramaniam, Hai Phuong
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AssigneeeSilicon Corporation
InventorsPrasad Subramaniam, Hai Phuong
Estimating the term…
Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.
A method performed by a computer system for optimizing a design point for an integrated circuit design, the method comprising:
A non-transitory computer-readable storage medium storing executable computer program instructions for optimizing a design point for an integrated circuit design, the instructions executable by a processor and causing the processor to perform a method comprising:
Dependencies are inferred from the claim text.