Transistor plasma charging eliminator
OwnerWallace W Lininventor
Life of this patent
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Abstract
An integrated-circuit design tool system capable of minimizing a plasma induced charging effect to a transistor in a plasma-based process performed for a dielectric layer on a metal layer comprises a pre-processing unit, a charging evaluator engine, a charging eliminator engine, a post-processing unit, and a non-transitory computer readable medium.
Claims14
A computer-implemented method capable of minimizing a plasma-induced charging effect to a transistor of an integrated circuit design in a plasma-based process for a dielectric layer performed on a metal layer above the transistor, comprising:
- a non-transitory computer readable medium comprising
- a set of computer instructions when executed by a computer system
- causing the system to execute the tasks;
- a charging evaluator engine incorporating comprehensive physical models governing multiple-terminal transistor plasma-charging behaviors;
- the charging evaluator engine further comprising:
- receiving an input related to a transistor characteristics, a plasma characteristics and an interconnect characteristics;
- and
- performing charging evaluation analysis for the transistor by calculating a potential at a gate terminal and a remaining terminal including a source, drain and n-well terminal;
- a charging eliminator engine incorporating comprehensive physical models governing multiple-terminal transistor plasma-charging behaviors;
- the charging eliminator engine further comprising:
- calculating difference in potential between a gate terminal and a remaining terminal of the transistor;
- determining whether an absolute value of the potential at the gate terminal is larger than an absolute value of the potential at the remaining terminal and the difference in potential between the gate terminal and the remaining terminal exceeds a degradation threshold;
- preparing a first alternative requiring downsizing a metal area for the gate terminal, and a second alternative requiring attachment of a protection device to the gate terminal and determining a size parameter of the protection device
- when the absolute value of the potential at the gate terminal is larger than the absolute value of the potential at the remaining terminal and the difference in potential between the gate terminal and the remaining terminal exceeds the degradation threshold;
- and
- performing manufacturing process based on minimized plasma-induced charging effect to the transistor of the integrated circuit design.
A computer system capable of minimizing a plasma-induced charging effect to a transistor of an integrated circuit design in a plasma-based process for a dielectric layer performed on a metal layer above the transistor, comprising a transistor plasma charging eliminator, wherein the transistor plasma charging eliminator comprising:
- a non-transitory computer readable medium comprising
- a set of computer instructions when executed by the computer system
- causing the system to execute the tasks;
- a charging evaluator engine incorporating comprehensive physical models governing multiple-terminal transistor plasma-charging behaviors;
- the charging evaluator engine further comprising:
- receiving an input related to a transistor characteristics, a plasma characteristics and an interconnect characteristics;
- and
- performing charging evaluation analysis for the transistor by calculating a potential at a gate terminal and a remaining terminal including a source, drain and n-well terminal;
- and
- a charging eliminator engine incorporating comprehensive physical models governing multiple-terminal transistor plasma-charging behaviors;
- the charging eliminator engine further comprising:
- calculating difference in potential between a gate terminal and a remaining terminal of the transistor;
- determining whether an absolute value of the potential at the gate terminal is larger than an absolute value of the potential at the remaining terminal and the difference in potential between the gate terminal and the remaining terminal exceeds a degradation threshold;
- preparing a first alternative requiring downsizing a metal area for the gate terminal, and a second alternative requiring attachment of a protection device to the gate terminal and determining a size parameter of the protection device when the absolute value of the potential at the gate terminal is larger than the absolute value of the potential at the remaining terminal and the difference in potential between the gate terminal and the remaining terminal exceeds the degradation threshold;
- and
- performing manufacturing process based on minimized plasma-induced charging effect to the transistor of the integrated circuit design.
Dependencies are inferred from the claim text.