Area-efficient memory mapping techniques for programmable logic devices

#The present invention relates generally to programmable logic devices and, more particularly, to implementing user-defined memories in such devices.

#Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded memories, embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.

#Many PLDs today include dedicated memory resources to facilitate efficient implementation of memory components such as random access memories (RAMs), read only memories (ROMs), and first-in first-out (FIFO) memories as may be needed in the user designs. Such dedicated memory resources, also referred to as embedded block RAMs (EBRs) or embedded memory blocks, are typically embedded in PLDs as one or more blocks of static RAM (SRAM), dynamic RAM (DRAM), and/or flash memory that can be configured together with other configurable resources of PLDs to implement memory components having desired functionalities.

#FIG. 1 illustrates a block diagram of a programmable logic device (PLD) in accordance with an embodiment of the disclosure.

#FIG. 2 illustrates a block diagram of an embedded block RAM (EBR) of a PLD in accordance with an embodiment of the disclosure.

#FIG. 3 illustrates a block diagram of a programmable logic block (PLB) of a PLD in accordance with an embodiment of the disclosure.

#Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

#In accordance with various embodiments set forth herein, techniques are provided to implement user-specified memory components (e.g., logical memories) by programmable logic devices (PLDs) having embedded block RAMS (EBRs). In particular, according to various embodiments of the disclosure, a logical memory in a design for a PLD may be mapped to EBRs to implement the logical memory in an area-efficient manner, such that the PLD configured with the design may require less EBRs and/or less of other PLD resources to implement the logical memory than would be possible with conventional mapping techniques. For example, improved logical memory mapping techniques according to one or more embodiments of the disclosure may include dividing a logical memory into a main area and a subarea (e.g., the remainder of the logical memory, excluding the main area) in a hierarchical manner for a more flexible and area-efficient mapping of the logical memory onto EBRs configured in a combination of different depth-width configurations, as opposed to treating the logical memory as one flat, monolithic area.

#In one or more embodiments, a computer-implemented method includes determining a main area of a logical memory that can be fully mapped to a first one or more EBRs configured in a first depth-width configuration, mapping the main area to the first one or more EBRs, and mapping the remainder of the logical memory to a second one or more EBRs configured in a second or more depth-width configurations. The mapping of the remainder of the logical memory may be performed hierarchically by a recursive process in some embodiments. The depth-width configurations and the corresponding mapping may be selected according to an efficiency metric, such as a memory area efficiency metric that is indicative of the aggregate size of the EBRs and other PLD resources that may be consumed to implement the logical memory. In some embodiments, the computer-implemented method may further include determining whether the mapping of the logical memory would lead to unbalanced utilization of EBRs and other PLD resources, and rebalancing if needed by replacing one or more EBRs in the mapping with other PLD components such as programmable logic blocks (PLBs) configured as memories.