System and method for efficient statistical timing analysis of cycle time independent tests

A system for statistical static timing analysis (SSTA) of a digital electronic design, the system comprising:

• one or more computer processors, one or more computer-readable storage media, and program instructions stored on the one or more computer-readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising:
• program instructions to propagate, using a computer, a signal label from a signal source to a cycle time dependent timing test, the signal label comprising at least one of:
• a signal source identifier, and
• a signal path cycle adjust information;
• program instructions to identify, at each input of the cycle time dependent timing test, which timing values of the signal label are needed to compute a downstream cycle time independent timing test;
• program instructions to propagate back from the cycle time dependent timing test to the signal source a flag indicating the identified timing values of the signal label needed to compute the downstream cycle time independent timing test;
• program instructions to compute timing data only for the identified values of the signal label which are needed to compute the downstream cycle time independent timing test;
• program instructions to generate a final circuit design based on the computed timing data;
• and
• program instructions to cause the final circuit design to be fabricated.