Dynamic fault model generation for diagnostics simulation and pattern generation

A computer program product for diagnostics simulation and pattern generation, the computer program product comprising:

• a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising:
• receiving, by the processing circuit, inline fabrication parametric data, wherein the inline fabrication parametric data is received for a device under test, wherein the inline fabrication parametric data is a collection of physical measurements associated with one or more components made on the device under test during stages of building process layers;
• generating, by the processing circuit, test patterns based on the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data;
• generating a fault model of defects comprising values according to the inline fabrication parametric data, the values of the fault model configured to be utilized in execution of the test patterns;
• running, by the processing circuit, a simulation of the device under test using the results and the inline fabrication parametric data, to thereby detect a location of one or more defects in the device under test, wherein the location is configured to be provided to physical failure analysis for disassembly of the device under test.

A computer system for dynamic complex fault model generation for diagnostics simulation and pattern generation, the system comprising:

• a memory;
• and
• a processor, communicatively coupled to the memory, the computer system configured to perform a method comprising:
• receiving, by the processor, inline fabrication parametric data, wherein the inline fabrication parametric data is received for a device under test, wherein the inline fabrication parametric data is a collection of physical measurements made on the device under test during stages of building process layers of the device under test;
• generating, by the processor, test patterns based on the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data;
• generating a fault model of defects comprising values according to the inline fabrication parametric data, the values of the fault model configured to be utilized in execution of the test patterns;
• and
• running, by the processor, a simulation of the device under test using the results and the inline fabrication parametric data, to thereby detect a location of one or more defects in the device under test, wherein the location is configured to be provided to physical failure analysis for disassembly of the device under test.