Efficient waveform generation for emulation
AssigneeSynopsys, Inc.
InventorsLudovic Marc Larzul, Alexander Rabinovitch
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Abstract
An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.
Claims20
A computer-implemented process executing on a host system for reducing bandwidth between the host system and an emulator, the process comprising:
- receiving, at the host system from the emulator, a first signal traced by the emulator based on emulation of a design under test (DUT), the DUT corresponding to a design of an integrated circuit (IC), the DUT comprising a plurality of sections, the emulator configured to implement the plurality of sections of the DUT, and the host system having a plurality of section files each corresponding to a respective one of the plurality of sections of the DUT;
- receiving, at the host system, a request for a second signal of the DUT not traced by the emulator;
- identifying, by the host system, from the plurality of sections, at least one section of the DUT that when simulated in combination with the first signal will generate the second signal;
- retrieving, by the host system, at least one of a plurality of section files that describes the at least one identified section to simulate the at least one identified section using, at least in part, the first signal received from the emulator;
- and
- generating, by the host system, the second signal.
A non-transitory computer readable medium storing instructions, the instructions when executed by a host system cause the host system to:
- receive, at the host system from an emulator, a first signal traced by the emulator based on emulation of a design under test (DUT), the DUT corresponding to a design of an integrated circuit (IC) to be tested, the DUT comprising a plurality of sections, and the host system having a plurality of section files each corresponding to a respective one of the plurality of sections of the DUT implemented in the emulator;
- receive, at the host system, a request for a second signal, the second signal for evaluating a function of the DUT not traced by the emulator;
- determine, by the host system, from the plurality of sections of the DUT, a subset of sections of the DUT to simulate to generate the second signal;
- simulate, by the host system, the subset of sections based on the first signal;
- and
- generate, by the host system, the second signal based on the simulation of the subset of sections.
A computer-implemented process that, when invoked upon receipt of a design under test (DUT) to emulate, executes on a host system, the process comprising:
- receiving, at a host system from an emulator, a first signal traced by the emulator based on emulation of the DUT, the DUT corresponding to a design of an integrated circuit (IC) to be tested, the DUT comprising a plurality of sections, the emulator configured to implement the plurality of sections of the DUT, and the host system having a plurality of section files each corresponding to a respective one of the plurality of sections of the DUT;
- receiving, at the host system, a request for a second signal, the second signal for evaluating a function of the DUT not traced by the emulator;
- determining, by the host system, from the plurality of sections of the DUT, a subset of sections of the DUT to simulate to generate the second signal;
- simulating, by the host system, the subset of sections based on the first signal;
- and
- generating, by the host system, the second signal based on the simulation of the subset of sections.
Dependencies are inferred from the claim text.