Techniques for scalable endpoint addressing for parallel applications
AssigneeIntel Corporation
InventorsKeith Underwood, Charles F. Giefer, David Addison
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AssigneeIntel Corporation
InventorsKeith Underwood, Charles F. Giefer, David Addison
Estimating the term…
Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.
A method for performing inter-process communication between nodes of a multi-node system, the method comprising:
A system comprising:
A non-transitory computer-readable medium having a plurality of instructions encoded thereon that when executed by at least one processor cause a process to be carried out, the process comprising:
A system comprising:
Dependencies are inferred from the claim text.