Techniques for handling interrupts in a processing unit using virtual processor thread groups and software stack levels

A processing unit for a multithreaded data processing system, the processing unit comprising:

• an interrupt source controller (ISC);
• and
• an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
• receive an event notification message (ENM) from the ISC, wherein the ENM specifies a level, an event target number, and a number of bits to ignore;
• determine a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted;
• and
• in response to one or more virtual processor threads in the group of virtual processor threads being available to service an interrupt associated with the ENM, select a single virtual processor thread from the one or more virtual processor threads to service the interrupt.

A design structure tangibly embodied in a computer-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• an interrupt source controller (ISC);
• and
• an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
• receive an event notification message (ENM) from the ISC, wherein the ENM specifies a level, an event target number, and a number of bits to ignore;
• determine a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted;
• and
• in response to one or more virtual processor threads in the group of virtual processor threads being available to service an interrupt associated with the ENM, select a single virtual processor thread from the one or more virtual processor threads to service the interrupt.