Hazard checking control within interconnect circuitry
AssigneeArm Limited
InventorsAndrew David Tune, Daniel Sara, Sean James Salisbury, Arthur Laughton, Peter Andrew Riocreux
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AssigneeArm Limited
InventorsAndrew David Tune, Daniel Sara, Sean James Salisbury, Arthur Laughton, Peter Andrew Riocreux
Estimating the term…
A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.
Interconnect circuitry for communicating access transactions between one or more transaction sources and one or more transaction destinations, said interconnect circuitry comprising:
Interconnect circuitry for communicating access transactions between one or more transaction sources and one or more transaction destinations, said interconnect circuitry comprising:
A method of operating interconnect circuitry for communicating access transactions between one or more transaction sources and one or more transaction destinations, said method comprising the steps of:
Dependencies are inferred from the claim text.