Efficiently generating selection masks for row selections within indexed address spaces

An indexed array circuit for efficiently generating selection masks for row selections within an indexed address space, comprising:

• a means for performing, for each indexed array row of a plurality of indexed array rows ordered in a logical sequence, a first plurality of parallel comparisons of a plurality of subsets of bits of a logical address of the indexed array row with a corresponding plurality of subsets of bits of a start indicator that indicates a start indexed array row of a row selection within the plurality of indexed array rows;
• a means for performing, for each indexed array row of the plurality of indexed array rows ordered in the logical sequence, a second plurality of parallel comparisons of the plurality of subsets of bits of the logical address of the indexed array row with a corresponding plurality of subsets of bits of an end indicator that indicates an end indexed array row of the row selection within the plurality of indexed array rows;
• a means for generating, for each indexed array row of the plurality of indexed array rows ordered in the logical sequence, a selection mask indicator that indicates whether the indexed array row is within the row selection, based on the first plurality of parallel comparisons and the second plurality of parallel comparisons;
• and
• a means for aggregating the plurality of generated selection mask indicators into a selection mask.

A method for efficiently generating selection masks for row selections within an indexed address space, comprising:

• for each indexed array row of a plurality of indexed array rows ordered in a logical sequence:
• performing, by a row-level compare circuit of an indexed array circuit, a first plurality of parallel comparisons of a plurality of subsets of bits of a logical address of the indexed array row with a corresponding plurality of subsets of bits of a start indicator that indicates a start indexed array row of a row selection within the plurality of indexed array rows;
• performing, by the row-level compare circuit of the indexed array circuit, a second plurality of parallel comparisons of the plurality of subsets of bits of the logical address of the indexed array row with a corresponding plurality of subsets of bits of an end indicator that indicates an end indexed array row of the row selection within the plurality of indexed array rows;
• and
• generating, by the row-level compare circuit of the indexed array circuit, a selection mask indicator that indicates whether the corresponding indexed array row is within the row selection, based on the first plurality of parallel comparisons and the second plurality of parallel comparisons;
• and
• aggregating, by the indexed array circuit, the plurality of generated selection mask indicators into a selection mask.