Cache memory system using a tag comparator to determine update candidates and operating method thereof

A cache memory apparatus comprising:

• a data memory configured to store pieces of cache data corresponding to pieces of data stored in a main memory;
• a tag memory configured to store pieces of tag data respectively corresponding to the pieces of the cache data, each of the pieces of the tag data comprising N bits;
• a tag comparator configured to
• calculate a difference between upper K bits, wherein 1≦K<N, of each of the pieces of the tag data corresponding to a set address that is received with upper K bits of a tag address that is received, the tag address comprising N bits;
• compare the tag address and each of the pieces of the tag data, and
• determine whether there is a cache hit or a cache miss based on results of the comparison;
• and
• an update controller configured to, in response to the cache miss being determined,
• determine a piece among the pieces of the cache data as an update candidate based on the difference, and
• update the update candidate with new data,
• wherein the update controller is configured to, in response to the cache memory apparatus receiving data requests, each having a same set address:
• determine, for each piece of data of the data requests, whether each piece of the cache data is an update candidate based on the result of the comparison of the upper K bits of the tag address that is received for each of the pieces of the data and the upper K bits of each of the pieces of tag data;
• and
• update, with new data, a piece among the pieces of the cache data that is determined as an update candidate the most.

A method of operating a cache memory apparatus, the method comprising:

• comparing upper K bits, wherein 1≦K<N, of each of pieces of tag data corresponding to a set address that is received with upper K bits of a tag address that is received, the pieces of the tag data respectively corresponding to pieces of cache data as the set, each of the pieces of the tag data comprising N bits, the tag address comprising N bits, and the pieces of the cache data corresponding to pieces of data;
• comparing other (N-K) bits of each of the pieces of the tag data with other (N-K) bits of the tag address, and
• determining whether there is a cache hit or a cache miss based on results of the comparisons;
• and
• in response to the cache miss being determined, determining a piece among the pieces of the cache data as an update candidate based on the result of the comparison of the upper K bits of each of the pieces of the tag data and the upper K bits of the tag address, and updating the update candidate with new data,
• wherein in response to receiving data requests, each having a same set address:
• the determining of the piece of the cache data as the update candidate comprises determining, for each piece of data of the data requests, whether each piece of the cache data is an update candidate based on the result of the comparison of the upper K bits of the tag address that is received for each of the pieces of the data and the upper K bits of each of the pieces of tag data;
• and
• the updating of the update candidate comprises updating, with new data, a piece among the pieces of the cache data that is determined as an update candidate the most.

A method of operating a cache memory apparatus, the method comprising:

• calculating a difference between upper K bits, wherein 1≦K<N, of each of pieces of tag data corresponding to a set address that is received and upper K bits of a tag address that is received, the pieces of the tag data respectively corresponding to pieces of cache data as the set, each of the pieces of the tag data comprising N bits, the tag address comprising N bits, and the pieces of the cache data corresponding to pieces data;
• comparing the tag address and each of the pieces of the tag data, and
• determining whether there is a cache hit or a cache miss based on results of the calculation and comparison;
• and
• in response to the cache miss being determined, determining a piece among the pieces of the cache data as an update candidate based on the difference, and updating the update candidate with new data,
• wherein in response to receiving data requests, each having a same set address:
• the determining of the piece of the cache data as the update candidate, comprises determining, for each piece of data of the data requests, whether each piece of the cache data is an update candidate based on the result of the comparison of the upper K bits of the tag address that is received for each of the pieces of the data and the upper K bits of each of the pieces of tag data;
• and
• the updating of the update candidate comprises updating, with new data, a piece among the pieces of the cache data that is determined as an update candidate the most.

A cache memory apparatus comprising:

• a tag comparator configured to
• compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received,
• compare other bits of each of the pieces of the tag data with other bits of the tag address, and
• determine whether there is a cache hit or a cache miss based on results of the comparisons;
• and
• an update controller configured to, in response to the cache miss being determined,
• determine, as an update candidate, a piece among the pieces of the cache data included in the set and corresponding to the pieces of the tad data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and
• update the update candidate with new data,
• wherein the update controller is configured to, in response to the cache memory apparatus receiving data requests, each having a same set address:
• determine, for each piece of data of the data requests, whether each piece of the cache data is an update candidate based on the result of the comparison of the upper K bits of the tag address that is received for each of the pieces of the data and the upper K hits of each of the pieces of tag data;
• and
• update, with new data, a piece among the pieces of the cache data that is determined as an update candidate the most.

A cache memory apparatus comprising:

• a data memory configured to store pieces of cache data corresponding to pieces of data stored in a main memory;
• a tag memory configured to store pieces of tag data respectively corresponding to the pieces of the cache data;
• a tag comparator configured to determine whether there is a cache hit or a cache miss by comparing each of the pieces of the tag data with a tag address that is received, wherein the comparing each of the pieces of the tag data with the tag address comprises comparing upper K bits of each of the pieces of the tag data with upper K bits of a tag address and comparing other (N-K) bits of each of the pieces of the tag data with other (N-K) bits of the tag address, and
• an update controller configured to determine a cache data to be updated based on results of the comparison of the upper K bits of each of the pieces of the tag data and the upper K bits of the tag address,
• wherein the update controller is configured to, in response to the cache memory apparatus receiving data requests, each having a same set address:
• determine, for each piece of data of the data requests, whether each piece of the cache data is an update candidate based on the result of the comparison of the upper K bits of the tag address that is received for each of the pieces of the data and the upper K bits of each of the pieces of tag data;
• and
• update, with new data, a piece among the pieces of the cache data that is determined as an update candidate the most.