Light-weight on-chip signal monitor with integrated memory management and data collection

An on-chip signal monitor comprising:

• a clock and data recovery (CDR) unit that provides a reference clock signal;
• a state machine that includes a sequencing logic, the sequencing logic configured to set a sample gate signal to a first level to initiate each sample acquisition, the sequencing logic configured to trigger an update of a digitized time value;
• a trigger flip flop that connects to the CDR unit to receive the reference clock signal and the sequencing logic to receive the sample gate signal, the trigger flip flop configured to pass a rising edge of the reference clock signal to an input of a programmable delay chain responsive to the sample gate signal being set to the first level;
• the programmable delay chain that receives the digitized time value and outputs a delayed rising edge to a sample-and-hold circuit at a time slice window determined by the digitized time value;
• a sample capture unit that includes:
• the sample-and-hold circuit that captures and integrates an input signal over the time slice window to output an average voltage of the input signal responsive to the delayed rising edge;
• and
• an analog-to-digital converter (ADC) that receives the average voltage of the input signal at the time slice window and digitizes the average voltage of the input signal to a digitized amplitude value;
• an address generator that uses the digitized time value and the digitized amplitude value to form an address of an accumulator register located in a memory;
• and
• a load-increment-store logic that fetches a value of the accumulator register from the address of the memory, increments the value by 1, and stores the incremented value in the address.

An on-chip signal monitor comprising:

• a clock and data recovery (CDR) unit that provides a reference clock signal;
• a state machine that includes a sequencing logic, the sequencing logic configured to set a sample gate signal to a first level to initiate each sample acquisition, the sequencing logic configured to trigger an update of a digitized time value and a digitized amplitude value;
• a trigger flip flop that connects to the CDR unit to receive the reference clock signal and the sequencing logic to receive the sample gate signal, the trigger flip flop configured to pass a rising edge of the reference clock signal to an input of a programmable delay chain responsive to the sample gate signal being set to the first level;
• the programmable delay chain that receives the digitized time value and outputs a delayed rising edge to a sample capture unit at a time slice window determined by the digitized time value;
• the sample capture unit that, responsive to the delayed rising edge, captures a sample from an input signal if the sample is within the time slice window and an amplitude slice window determined by the digitized amplitude value;
• an address generator that uses the digitized time value and the digitized amplitude value to form an address of an accumulator register located in a memory;
• and
• a load-increment-store logic that fetches a value of the accumulator register from the address of the memory, increments the value by 1, and stores the incremented value in the address.

A method of acquiring samples using an automatic signal monitor, the method comprising:

• setting a sample gate signal to a first level to initiate sample acquisition;
• capturing an input signal over a time slice window to output an average voltage of the input signal in the time slice window, wherein the time slice window is determined by a digitized time value stored in a counter;
• digitizing the average voltage of the input signal to a digitized amplitude value;
• forming an address of an accumulator register based on the digitized time value and the digitized amplitude value;
• fetching a value stored in the accumulator register using the address;
• incrementing the value by 1;
• and
• storing the value in the accumulator register.

A method of acquiring samples using an automatic signal monitor, the method comprising:

• setting a sample gate signal to a first level to initiate sample acquisition;
• capturing a sample within a time slice window determined by a digitized time value and an amplitude slice window determined by a digitized amplitude value, wherein the digitized time value and the digitized amplitude value are stored in a counter;
• generating a sample-in-window signal with a trigger level to trigger an update of an accumulator register determined by the digitized time value and the digitized amplitude value;
• forming an address of the accumulator register based on the digitized time value and the digitized amplitude value;
• fetching a value stored in the accumulator register using the address;
• incrementing the value by 1;
• and
• storing the value in the accumulator register.