US 9,852,006 B2 · Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Abstract

Embodiments of the invention relate to a neural network circuit comprising a memory block for maintaining neuronal data for multiple neurons, a scheduler for maintaining incoming firing events targeting the neurons, and a computational logic unit for updating the neuronal data for the neurons by processing the firing events. The network circuit further comprises at least one permutation logic unit enabling data exchange between the computational logic unit and at least one of the memory block and the scheduler. The network circuit further comprises a controller for controlling the computational logic unit, the memory block, the scheduler, and each permutation logic unit.

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Drawings

Claims20

Dependent claims

A neural network circuit, comprising:

a memory block partitioned into multiple memory sub-blocks, each memory sub-block corresponding to a core circuit of multiple neurosynaptic core circuits, and each memory sub-block maintaining neuronal data for multiple neurons of a corresponding core circuit;
a scheduler comprising multiple bit maps, each bit map corresponding to a core circuit of said core circuits, and each bit map indicative of one or more incoming firing events targeting one or more neurons of a corresponding core circuit;
a computational logic unit comprising a set of input registers, said computational logic unit configured to load neuronal data for multiple neurons of a core circuit from a corresponding memory sub-block of said memory block into said set of input registers, and update said neuronal data in said corresponding memory sub-block by processing a corresponding bit map of said scheduler to integrate one or more incoming firing events targeting one or more neurons of said core circuit;
and
a controller configured to control execution of said computational logic unit and access to said memory block and said scheduler.

2 more elements

A method for consolidating neuronal data for multiple neurons, comprising:

maintaining neuronal information in a memory block partitioned into multiple memory sub-blocks, each memory sub-block corresponding to a core circuit of multiple neurosynaptic core circuits, and each memory sub-block maintaining neuronal data for multiple neurons of a corresponding core circuit;
maintaining incoming firing event information in a scheduler comprising multiple bit maps, each bit map corresponding to a core circuit of said core circuits, and each bit map indicative of one or more incoming firing events targeting one or more neurons of a corresponding core circuit;
updating said neuronal information by processing said incoming firing event information via a computational logic unit comprising a set of input registers, said computational logic unit configured to load neuronal data for multiple neurons of a core circuit from a corresponding memory sub-block of said memory block into said set of input registers, and update said neuronal data in said corresponding memory sub-block by processing a corresponding bit map of said scheduler to integrate one or more incoming firing events targeting one or more neurons of said core circuit;
and
controlling, via a controller, execution of said computational logic unit and access to said memory block and said scheduler.

2 more elements

A computer program product for consolidating neuronal data for multiple neurons, the computer program product comprising a non-transitory computer-useable storage medium having program code embodied therewith, the program code being executable by a computer to:

maintain neuronal information in a memory block partitioned into multiple memory sub-blocks, each memory sub-block corresponding to a core circuit of multiple neurosynaptic core circuits, and each memory sub-block maintaining neuronal data for multiple neurons of a corresponding core circuit;
maintain incoming firing event information in a scheduler comprising multiple bit maps, each bit map corresponding to a core circuit of said core circuits, and each bit map indicative of one or more incoming firing events targeting one or more neurons of a corresponding core circuit;
update said neuronal information by processing said incoming firing event information via a computational logic unit comprising a set of input registers, said computational logic unit configured to load neuronal data for multiple neurons of a core circuit from a corresponding memory sub-block of said memory block into said set of input registers, and update said neuronal data in said corresponding memory sub-block by processing a corresponding bit map of said scheduler to integrate one or more incoming firing events targeting one or more neurons of said core circuit;
and
control, via a controller, execution of said computational logic unit and access to said memory block and said scheduler.

2 more elements

Dependencies are inferred from the claim text.

Description9,762 words

Summary441 words

#Embodiments of the invention relate to neuromorphic and synaptronic computation and in particular, consolidating multiple neurosynaptic core circuits into one reconfigurable memory block.

#Neuromorphic and synaptronic computation, also referred to as artificial neural networks, are computational systems that permit electronic systems to essentially function in a manner analogous to that of biological brains. Neuromorphic and synaptronic computation do not generally utilize the traditional digital model of manipulating 0s and 1s. Instead, neuromorphic and synaptronic computation create connections between processing elements that are roughly functionally equivalent to neurons of a biological brain. Neuromorphic and synaptronic computation may comprise various electronic circuits that are modeled on biological neurons.

#In biological systems, the point of contact between an axon of a neuron and a dendrite on another neuron is called a synapse, and with respect to the synapse, the two neurons are respectively called pre-synaptic and post-synaptic. The essence of our individual experiences is stored in conductance of the synapses. The synaptic conductance changes with time as a function of the relative spike times of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.

Brief description of the drawings17 figures

#FIG. 1 illustrates a neurosynaptic core circuit, in accordance with an embodiment of the invention;

#FIG. 2 illustrates an example reconfigurable neurosynaptic network circuit, in accordance with an embodiment of the invention;

#FIG. 3 illustrates an example configuration for a neurosynaptic network circuit, wherein, in the configuration, the network circuit represents a single core circuit, in accordance with an embodiment of the invention;

Detailed description8,836 words

#Embodiments of the invention relate to neuromorphic and synaptronic computation and in particular, consolidating multiple neurosynaptic core circuits into one reconfigurable memory block. The memory block maintains neuronal data for neurons of the core circuits. Different types of neuronal data, such as synaptic connectivity information, neuron parameters, and neuronal states, may be mapped to different locations of the memory block, and/or allocated different amounts of memory from the memory block.

#In one embodiment, a neurosynaptic system comprises a system that implements neuron models, synaptic models, neural algorithms, and/or synaptic algorithms. In one embodiment, a neurosynaptic system comprises software components and/or hardware components, such as digital hardware, analog hardware or a combination of analog and digital hardware (i.e., mixed-mode).

#The term electronic neuron as used herein represents an architecture configured to simulate a biological neuron. An electronic neuron creates connections between processing elements that are roughly functionally equivalent to neurons of a biological brain. As such, a neuromorphic and synaptronic computation comprising electronic neurons according to embodiments of the invention may include various electronic circuits that are modeled on biological neurons. Further, a neuromorphic and synaptronic computation comprising electronic neurons according to embodiments of the invention may include various processing elements (including computer simulations) that are modeled on biological neurons. Although certain illustrative embodiments of the invention are described herein using electronic neurons comprising electronic circuits, the present invention is not limited to electronic circuits. A neuromorphic and synaptronic computation according to embodiments of the invention can be implemented as a neuromorphic and synaptronic architecture comprising circuitry, and additionally as a computer simulation. Indeed, embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements.

Facts

Application

14/229,760Filed 28 Mar 2014

Published

US 2016/0321537 A13 Nov 2016

Granted

26 Dec 2017

Term ends

27 Oct 2036

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 944 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification5 codes

G06F 9/50
Multiprogramming arrangements: allocation of resources, e.g. of the central processing unit [CPU]
G06N 3/049
Architecture, e.g. interconnection topology: temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G06F
Computing and data processing

Timeline

28 Mar 2014Application filedUS 14/229,760
28 Mar 2014Assigned to International Business Machines Corporationassignment of assignor's interest
3 Nov 2016PublishedUS 2016/0321537 A1
26 Dec 2017GrantedUS 9,852,006 B2
12 Oct 2026TodayWithin its term
27 Oct 2036Term endsEstimated, includes 944 days of adjustment

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Life of this patent

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description9,762 words

Drawings

Classification5 codes

Life of this patent

Description9,762 words