Apparatus and method for combining thread warps with compatible execution masks for simultaneous execution and increased lane utilization

#The invention relates to single-instruction, multiple-data (SIMD) processors, such as graphics processing units (GPU), which, from a programmer's stand point, can also be considered as single-program, multiple-data (SPMD) or single-instruction, multiple-thread (SIMT) processors.

#In the graphics processing domain, many tasks involve applying a same algorithm to multiple pixels, such as an image line or a macroblock. Therefore graphics processors were originally designed to apply a single instruction to multiple pixels at the same time in order to increase throughput. Such graphics processors thus include multiple hardware execution units, generally pipelined, where a single instruction is applied simultaneously to the data present in each execution unit.

#A same execution unit is usually assigned to a same program thread and the multiple threads processed in parallel lockstep in the execution units are sometimes referred to as a “warp”. The data at the same state of processing in the units will be referred to as a data “wave”.

#FIG. 1 is a block diagram of an exemplary SPMD processor system.

#FIGS. 2A to 2C are graphs illustrating an exemplary manner of handling branches occurring in multiple threads of a warp processed by the system of FIG. 1.

#FIG. 3 is a block diagram of an embodiment of an N-instruction, multiple-data processor system, exemplified as a two-instruction, multiple-data processor system.

#FIG. 1 is a block diagram of an exemplary single-program, multiple-data processor system. It comprises a plurality of functional units FU to which a same instruction is broadcast by an instruction decode and issue unit 10. Moreover the functional units receive independent data, or a data wave, to operate on from a register file 12. The register file exchanges its data with a data memory location, usually a data cache memory 14. The data wave location in the register file is identified by the decode unit 10 from information carried in the instruction. The results produced by the functional units are written back in the register file, and, from there, into the data cache, if necessary.

#The instructions to execute are contained in an instruction memory location, usually an instruction cache memory 16. An instruction fetch unit 18 is configured to transfer an instruction identified by a program counter PC from the instruction cache to the decode unit 10. The instruction path is thus pipelined, i.e. several clock cycles will occur, typically in the order of ten, between the time an instruction is fetched by unit 18 and the time the corresponding result is produced by the functional units FU.

#A scheduler 20 is configured to select the sequence of instructions to execute by correspondingly updating the program counter PC. These instructions are retrieved from a warp pool 22, containing a snapshot of the execution state of a group of executable warps. In particular, the pool contains, for each warp, the program counter value of the next instruction to execute in the warp, an identification of the data wave to execute the instruction with, and an execution mask identifying the functional units that are to be used (indeed, as explained later, all functional units are not always used). The execution mask is placed in a mask stack 24 and is broadcast to all functional units when unit 10 broadcasts the corresponding instruction. The functional units identified by bits set to an active state in the mask will respond to the instruction, while the remaining units will stay idle.