US 9,851,974 B2 · Selective suppression of instruction cache-related directory access

Abstract

Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch; and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, and forcing for the next instruction an address match signal for the same cache line. The suppressing may include generating a known-to-hit signal where the next fetch is in the same cache line, and the last fetch is not a branch instruction, and issuing an instruction cache hit where a cache line segment of the same cache line having the next instruction has a valid validity bit, the valid validity bit having been retrieved and maintained based on a most-recent, instruction cache-directory-accessed fetch.

Claims16

Dependent claims

A method of processing an instruction fetch from an instruction cache, the method comprising:

determining for a next instruction fetch whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch from the instruction cache;
and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, forcing for the next instruction fetch an address match signal for the same cache line, and refraining from the suppressing where there has been an invalidation action against the same cache line, which causes the same cache line to no longer be valid, the invalidation action result in a known-to-hit signal being negated.

A system for processing an instruction fetch from an instruction cache, the system comprising:

a memory;
and a processor communicatively coupled to the memory, where the system performs a method comprising:
determining for a next instruction fetch whether the next instruction fetch in a same cache line of the instruction cache as a last instruction fetch from the instruction cache;
and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, forcing for the next instruction fetch an address match signal for the same cache line, and refraining from the suppressing where there has been an invalidation action against the same cache line, which causes the same cache line to no longer be valid, the invalidation action result in a known-to-hit signal being negated.

1 more element

Dependencies are inferred from the claim text.

Selective suppression of instruction cache-related directory access

Life of this patent

Selective suppression of instruction cache-related directory access

Life of this patent

Abstract

Claims16