Functional unit for instruction execution pipeline capable of shifting different chunks of a packed data operand by different amounts

#The field of invention relates generally to computing systems and more specifically to a functional unit an instruction execution pipeline that is capable of shifting different chunks of a packed data operand by different amounts.

#FIG. 1 shows a high level diagram of a processing core 100 implemented with logic circuitry on a semiconductor chip. The processing core includes a pipeline 101. The pipeline consists of multiple stages each designed to perform a specific step in the multi-step process needed to fully execute a program code instruction. These typically include at least: 1) instruction fetch and decode; 2) data fetch; 3) execution; 4) write-back. The execution stage performs a specific operation identified by an instruction that was fetched and decoded in prior stage(s) (e.g., in step 1) above) upon data identified by the same instruction and fetched in another prior stage (e.g., step 2) above). The data that is operated upon is typically fetched from (general purpose) register storage space 102. New data that is created at the completion of the operation is also typically “written back” to register storage space (e.g., at stage 4) above).

#The logic circuitry associated with the execution stage is typically composed of multiple “execution units” or “functional units” 103_1 to 103_N that are each designed to perform its own unique subset of operations (e.g., a first functional unit performs integer math operations, a second functional unit performs floating point instructions, a third functional unit performs load/store operations from/to cache/memory, etc.). The collection of all operations performed by all the functional units corresponds to the “instruction set” supported by the processing core 100.

#The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

#FIG. 1 shows an instruction execution pipeline;

#FIGS. 2a,b compare scalar and vector operations;

#FIG. 3a shows a depiction of a vector instruction that is able to select any contiguous group of bits in a chunk (e.g., quadword) of a first input packed data operand 301 and provide them as a particular element in a same positioned (“aligned”) chunk of a packed data resultant 303. The instruction is able to individually perform this operation for each element in the packed data resultant 303 such that each element's contiguous group of bits is individually selected from the first operand 301. The individual selections are specified in a second input packed data operand 302 that acts as a control element. Notably, there are no restrictions on the location of each selected group of bits within the first operand 301 other than being selected from within an aligned chunk and having a fixed width (e.g., the end of a selected group of contiguous bits need not be on a byte element boundary within a chunk).

#FIG. 3a pertains to an exemplary embodiment in which the underlying vector machine operates on 512 bit operands. The 512 bit resultant 303 is viewed as having eight 64 bit chunks 304_1 through 304_8 where each 64 bit chunk is further viewed as having eight 8 bit elements. The first input operand 301 is also viewed as having eight 64 bit chunks 305_1 through 305_8. The second input operand 302 is a control element that individually specifies, for each 8 bit element in a particular 64 bit chunk of the resultant 303, a contiguous group of 8 bits from the 64 bit chunk of the first input operand 301 that is aligned with the 64 bit chunk of the resultant 303.

#For example, 8 bit element 306 of resultant 303 is part of 64 bit chunk 304_8 in the resultant 303. The contents of 8 bit element 306 can therefore be any contiguous group of 8 bits from 64 bit chunk 305_8 of the first input operand 301 (chunk 305_8 of the first operand 301 being aligned with chunk 304_8 of the resultant 303). The specific contiguous group of 8 bits that are individually selected for 8 bit element 306 are uniquely identified in element 307 of the second input operand 302 (starting at bit “A” in chunk 305_8). Thus, each 8 bit element in the resultant 303 has a corresponding element in the second operand 303 that uniquely identifies what 8 bit segment of the same positioned chunk in the first operand 301 is to provide the 8 bit element in the resultant 303 with its content. This operational approach is taken for each 8 bit element in each 64 bit chunk of the resultant 303. For ease of drawing, only three actual selections are depicted in FIG. 3a (the pair of leftmost 8 bit elements in chunk 304_8 of the resultant and the leftmost 8 bit element in chunk 304_7 of the resultant).