Method and apparatus for performing reduction operations on a set of vector elements

A processor comprising:

• a value vector register to store a plurality of data element values to be reduced, wherein each of the data element values within the value vector register is associated with a single instruction multiple data (SIMD) lane in the processor;
• an index vector register to store a plurality of index values indicating which values in the value vector register are associated with one another;
• SIMD reduction logic to perform reduction operations on the data element values within the value vector register by combining data element values from the value vector register which are associated with one another as indicated by the index values in the index vector register, wherein performing the reduction operations further comprise:
• detecting conflicts across each of the lanes to generate conflict results and storing the conflict results in a conflict destination register, and
• marking each lane with the same index value as left and right children in their respective reduction trees to generate a bit sequence;
• and
• an accumulation vector register to store results of the reduction operations generated by the SIMD reduction logic.