Bit remapping mechanism to enhance lossy compression in floating-point applications

A method of reducing power transmitted over a memory to cache bus having a plurality of cache lines, the method comprising;

• rounding bits in least significant bit (LSB) positions of floating point (FP) numbers to a uniform binary value string;
• mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to expose a higher number of matching bit patterns between pairs of detected FP numbers to thereby increase compression ratios;
• and
• compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process.

An apparatus for of reducing power transmitted over a memory to cache bus having a plurality of cache lines, comprising:

• a detection component detecting floating point (FP) numbers in a dataset transmitted over a cache line of the plurality of cache lines;
• a rounding component rounding bits in least significant bit (LSB) positions of each detected FP number to a set binary value;
• and
• a mapping component mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each detected FP number to expose a higher number of matching bit patterns between pairs of detected FP numbers to thereby increase compression ratio of data flow in FP applications.