Flash memory chip processing

A non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by:

• attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value;
• sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples;
• defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell;
• determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample;
• and
• preventing a copyback operation when the reliability of the data sample is below a reliability threshold.

A semiconductor die that comprises a processor, a sampling circuit and a flash memory array;

• wherein the sampling circuit is configured to:
• (a) attempt, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value;
• (b) sample an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples;
• wherein the processor is configured to define a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell;
• (c) determine a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample;
• and
• (d) select between an execution of a copyback operation and a provision of the data sample to an external flash memory controller based upon the reliability of the data sample.

A method for sampling a flash memory cell that belongs to a die, the method comprising:

• performing a first attempt, during a first gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value;
• sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the first voltage gate change period to provide multiple first samples;
• and
• defining a first given sample of the first multiple samples as a first data sample that represents data stored in the flash memory cell;
• determining, by a processor that belongs to the die, a reliability of the first data sample based on one or more samples of the first multiple samples that differ from the first given sample;
• performing a second attempt, during a second gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first intermediate value to a third value;
• wherein the second attempt starts before a completion of the first attempt and when the gate voltage of the flash memory cell reached the first intermediate value;
• defining a second given sample of the second multiple samples as a second data sample that represents the data stored in the flash memory cell;
• determining, by the processor, a reliability of the second data sample based on one or more samples of the second multiple samples that differ from the second given sample;
• and
• preventing a copyback operation when the reliability of the first data sample or the second data sample is below a reliability threshold.