Two-stage read/write 3D architecture for memory devices

A memory device comprising:

• a memory cell array comprising a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells;
• a control circuit configured to perform a first read/write operation during a first time interval by writing a first data value to the first group of memory cells while concurrently reading a second data value from the second group of memory cells;
• wherein the control circuit is further configured to perform a second read/write operation during a second time interval by writing a third data value to the third group of memory cells while concurrently reading a fourth data value from the fourth group of memory cells, the second time interval being after the first time interval;
• and
• wherein the second data value and the fourth data value are collectively made up of N-bits and collectively correspond to an N-bit output data word provided onto output pins of the memory device at a time after the second time interval.

A memory device comprising:

• a first memory cell array on a first tier;
• a second memory cell array on a second tier, the second tier being arranged over the first tier, or vice versa;
• and
• a control circuit coupled to the first memory cell array and the second memory cell array, the control circuit being coupled to the first memory cell array via a first set of wordlines and a first set of bitlines, and being coupled to the second memory cell array via a second set of wordlines and a second set of bitlines;
• and
• wherein the control circuit is configured to read or write an N-bit word, which is presented to or received from pins of the memory device, wherein the N-bit word includes N/2 even bits which are written to or read from columns of memory cells in the first memory cell array via the first set of bitlines and includes N/2 odd bits which are written to or read from columns of memory cells in the second memory array via the second set of bitlines.