Random number generation in ferroelectric random access memory (FRAM)

A system comprising:

• a ferroelectric random access memory (FRAM) array comprising a plurality of two transistor, two capacitor (2T-2C) memory cells arranged in rows and columns;
• a processor configured to generate a random number using a set of 2T-2C memory cells from the FRAM array by:
• performing a write operation in a one transistor, one-capacitor (1T-1C) mode to write a uniform data pattern to the set of 2T-2C memory cells;
• after writing the uniform data pattern, performing a read operation in a 2T-2C mode on the set of 2T-2C memory cells to produce the random number.

A method for using n two transistor, two capacitor (2T-2C) ferroelectric memory cells to generate an n-bit random number, the method comprising:

• for each of the n 2T-2C ferroelectric memory cells, where n is an integer greater than or equal to 1:
• polarizing each of a first ferroelectric capacitor and a second ferroelectric capacitor of the 2T-2C ferroelectric memory cell to a first polarization state corresponding to a first logic value;
• providing, to a first input of a sense amplifier, a first signal corresponding to the first logic value on a first bit line coupled to the first ferroelectric capacitor;
• providing, to a second input of the sense amplifier, a second signal corresponding to the first logic value on a second bit line coupled to the second ferroelectric capacitor;
• and
• producing, using the sense amplifier, a random data bit having one of the first logic value or a second logic value in response to receiving the first and second signals.