Memory device, memory system and method of operating memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-Wan Nam, Doo-Hyun Kim, Dae-Seok Byeon, Chi-Weon Yoon
Life of this patent
Estimating the term…
Abstract
A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
Claims26
A three-dimensional (3D) memory device including a memory cell array, the memory cell array including a plurality of memory blocks, each of the memory blocks including a plurality of memory cell strings, each of the memory cell strings including a pillar extending in a direction vertical to a substrate and a plurality of transistors stacked along the pillar,
- the memory device comprising:
- a first block region including at least one memory block and having a first distance from a center of the memory cell array;
- a second block region including at least one memory block and having a second distance from the center of the memory cell array;
- and
- a control logic configured to store a first algorithm and a second algorithm, the first algorithm and the second algorithm being associated with the first block region and the second block region respectively, and further configured to control a first operation on the first block region using the first algorithm and a second operation on the second block region using the second algorithm respectively,
- wherein the first algorithm and the second algorithm are different when the first distance and the second distance are different.
A three-dimensional (3D) memory device including a memory cell array, the memory cell array including a plurality of memory blocks, each of the memory blocks including a plurality of memory cell strings, each of the memory cell strings including a pillar extending in a direction vertical to a substrate and a plurality of transistors stacked along the pillar,
- the memory device comprising:
- a first memory block having a first distance from a center of the memory cell array;
- a second memory block having a second distance from the center of the memory cell array;
- and
- a control logic configured to store a first algorithm and a second algorithm, the first algorithm and the second algorithm being associated with the first memory block and the second memory block respectively, and further configured to control a first operation on the first memory block using the first algorithm and a second operation on the second memory block using the second algorithm respectively,
- wherein the first algorithm and the second algorithm are different when the first distance and the second distance are different.
Dependencies are inferred from the claim text.