Concurrent memory operations for read operation preemption
AssigneeIntel Corporation
InventorsAnand S. Ramalingam, Pranav Kalavade, Aliasgar S. Madraswala
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsAnand S. Ramalingam, Pranav Kalavade, Aliasgar S. Madraswala
Estimating the term…
A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.
An apparatus for a non-volatile memory, comprising:
A method, comprising:
A system, comprising:
Dependencies are inferred from the claim text.