Semiconductor devices and semiconductor systems including the same
AssigneeSK hynix Inc.
InventorYoung Jun Yoon
Life of this patent
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Abstract
A semiconductor system includes a controller and a semiconductor device. The controller generates command signals, a composite control signal, and data signals. The semiconductor device generates a first mode signal and a second mode signal according to the command signals. The semiconductor device includes a write control circuit suitable for receiving the composite control signal and the data signals to determine an execution/non-execution of a data masking operation and a data bus inversion (DBI) operation when a write operation or a masking write operation is performed according to the first and second mode signals.
Claims32
A semiconductor system comprising:
- a controller suitable for generating command signals, a composite control signal and data signals;
- and
- a semiconductor device suitable for generating a first mode signal and a second mode signal according to the command signals,
- wherein the semiconductor device includes a write control circuit suitable for receiving the composite control signal and the data signals to determine an execution/non-execution of a data masking operation and a data bus inversion (DBI) operation when a write operation or a masking write operation is performed according to the first and second mode signals, and
- wherein the write control circuit selectively executes the data masking operation or the DBI operation according to a phase variation of the data signals outputted from the controller if the first mode signal and the second mode signal are enabled.
A semiconductor device comprising:
- a command decoder suitable for decoding command signals to generate a write command signal for a write operation, a masking write command signal for a masking write operation, and a mode register write command signal;
- a mode signal generator suitable for receiving the mode register write command signal to generate a first mode signal and a second mode signal from the command signals, for storing the first and second mode signals, and for outputting the first and second mode signals;
- and
- a write control circuit suitable for receiving a composite control signal and data signals to determine an execution/non-execution of a data masking operation and a data bus inversion (DBI) operation when the write operation or the masking write operation is performed according to the first and second mode signals,
- wherein the write control circuit selectively executes the data masking operation or the DBI operation according to a phase variation of the data signals outputted from a controller if the first mode signal and the second mode signal are enabled.
Dependencies are inferred from the claim text.