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US 9,851,900 B2Granted
Multiple memory rank system and selection method thereof
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt
Life of this patent
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AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt
Estimating the term…
A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.
A controller comprising:
A computer-readable storage medium having instructions stored thereon that, in response to execution by a processing device, causes the processing device to perform operations comprising:
A method comprising:
A system comprising:
Dependencies are inferred from the claim text.
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Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
Configuration or reconfiguration of storage systems: by changing the path, e.g. traffic rerouting, path reconfiguration
In-line storage system: single storage device
Addressing or allocation; Relocation: addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
About 8 years 6 months of term left · ends 8 May 2035 (estimated)
Memory systems, such as dual in-line memory modules (DIMMs), may include plural memory ranks. A memory rank may comprise plural memory devices simultaneously available to a controller in any manner, typically by asserting a common chip select (CS) signal. Typically, plural ranks mounted on a DIMM share command/address (CA) signals. Two or more ranks cannot be accessed simultaneously because although the data signals for each memory device on a rank are separate, the data signals are shared between ranks. Plural ranks may coexist on a single DIMM, e.g., one rank, two ranks, four ranks, and so on. Each rank may have any number of individual memory devices of a variety of technologies, e.g., dynamic random access memory (DRAM).
Each rank is typically uniquely associated with a CS signal. A controller may select a particular rank to receive and respond to the CA signals by asserting the CS signal associated with the particular rank. In a memory system in which a DIMM comprises a first rank and a second rank, a first CS signal runs from the controller to the first rank and a second CS signal runs from the controller to the second rank. A controller selects the first rank or the second rank by asserting the first CS signal or the second CS signal, respectively. An additional CS signal will be necessary for each additional rank added to the DIMM, which may be inefficient in some circumstances and may adversely impact DIMM board design, particularly pin out layout and usage at an interface to the controller.
FIG. 1 is a block diagram of a memory system according to an embodiment.
FIGS. 2A and 2B are timing diagrams associated with the memory system shown in FIG. 1.
FIGS. 3A and 3B are block diagrams of a logic circuit according to an embodiment of a memory device shown in FIG. 1.
Referring to FIG. 1, a memory system 100 comprises a controller 102 communicatively coupled to a first memory rank 110 and a second memory rank 120 through a command/address bus 104 and a data bus 106A-D. A person of ordinary skill in the art should recognize that memory system 100 may include other bus configurations, e.g., a command bus distinct from an address bus.
Generally, a memory rank such as first memory rank 110 and second memory rank 120 may comprise plural memory devices simultaneously available to a controller. In an embodiment, first memory rank 110 may comprise memory devices 112A, 112B, 112C, and 112D (collectively memory devices 112). Similarly, second memory rank 120 may comprise memory devices 122A, 122B, 122C, and 122D (collectively memory devices 122). A person of ordinary skill in the art should recognize that first memory rank 110 or second memory rank 112 may comprise any number of memory devices, including one, two, four, or eight memory devices or the like. Memory devices 112 or 122 may be dynamic random access memory (DRAM), flash memory, read only memory (ROM), ferroelectric RAM, resistive RAM, or the like.
Controller 102 applies commands and row and column addresses through command/address bus 104 to read data from or write data to first memory rank 110 or second memory rank 120. In a write access, controller 102 provides data to be written to first memory rank 110 or to second memory rank 120 through data bus 106A-D, with individual data bits DQ[0] on line 106A, DQ[1] on line 106B, DQ[2] on line 106C, and DQ[3] on line 106D. In a read access, data read from memory devices 112 on first memory rank 110 or data read from memory devices 122 on second memory rank 120 reaches controller 102 through data bus 106A-D.