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US 9,851,899 B2Granted
Nonvolatile memory system and sequential reading and programming methods thereof
AssigneeSK hynix Inc.
InventorByoung-Sung You
Life of this patent
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Abstract
A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.
Claims10
A nonvolatile memory system comprising:
- a first nonvolatile memory device including a first multi-level cell which stores M-bit data, M being an integer equal to or greater than 3, at a time and M number of first latches for respectively storing M-bit data on a single bit basis;
- a second nonvolatile memory device including a second multi-level cell which stores N-bit data, N being an integer equal to or greater than 3, at a time and N number of second latches for respectively storing N-bit data on a single bit basis;
- and
- a controller suitable for:
- sequentially latching M-bit data of the multi-level cell into the M number of first latches, respectively, during a first half read period of the first nonvolatile memory device, and sequentially outputting the latched M-bit data in the M number of first latches during a second half read period of the first nonvolatile memory device, and
- sequentially latching N-bit data of the multi-level cell into the N number of second latches, respectively, during a first half read period of the second nonvolatile memory device, and sequentially outputting the latched N-bit data in the N number of second latches during a second half read period of the second nonvolatile memory device,
- wherein the controller controls the first and second nonvolatile memory devices in a pipelining way such that the second half read period of the first nonvolatile memory device and the first half read period of the second nonvolatile memory device overlaps with each other.
4 more elements
A method for operating a nonvolatile memory system having first and second nonvolatile memory devices, the method comprising:
- sequentially latching M-bit data of a multi-level cell into a M number of first latches, respectively, during a first half read period of the first nonvolatile memory device, and sequentially outputting the latched M-bit data in the M number of first latches during a second half read period of the first nonvolatile memory device, and
- sequentially latching N-bit data of a multi-level cell into a N number of second latches, respectively, during a first half read period of the second nonvolatile memory device, and sequentially outputting the latched N-bit data in the N number of second latches during a second half read period of the second nonvolatile memory device,
- wherein the sequentially latching and outputting of the M-bit data and the sequentially latching and outputting N-bit data are performed in a pipelining way such that the second half read period of the first nonvolatile memory device and the first half read period of the second nonvolatile memory device overlaps with each other.
Dependencies are inferred from the claim text.