US 9,851,777 B2 · Power gating based on cache dirtiness

Abstract

Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Claims22

Dependent claims

A method comprising:

estimating a time to flush at least one cache that is used to cache data for access by a processor core of a processor system based on a cache dirtiness of the at least one cache,
wherein estimating the time to flush the at least one cache comprises estimating a total amount of information that needs to be written back to a backing store based on the cache dirtiness and estimating available bandwidth for writing information to the backing store;
and
selectively power gating the processor core based on a sum of time to flush said at least one cache and a time to save a state of the processor core.

1 more element

A processor system comprising:

a processor core;
at least one cache to cache data for access by the processor core;
analyzer logic to estimate a time to flush the at least one cache based on a cache dirtiness of the at least one cache, wherein the analyzer logic is configured to selectively power gate the processor core based on a sum of the time to flush said at least one cache and a time to save a state of the processor core;
and
a backing store to store information flushed from the at least one cache, wherein the analyzer logic is configured to estimate a total amount of information that needs to be written back to the backing store based on the cache dirtiness and estimate available bandwidth for writing information to the backing store.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/146,591Filed 2 Jan 2014

Published

US 2015/0185801 A12 Jul 2015

Granted

26 Dec 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
G06F 1/3225
Monitoring of peripheral devices: of memory devices
Y02D 10/00
Energy efficient computing
Y02D 30/50
Reducing energy consumption in communication networks: in wire-line communication networks, e.g. low power modes or reduced link rate

Power gating based on cache dirtiness

Life of this patent

Power gating based on cache dirtiness

Life of this patent

Abstract

Claims22