Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

An apparatus, comprising:

• means for counting, during a current program execution phase, a number of cycles in which a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss;
• means for measuring a stall fraction during the current program execution phase, wherein the measured stall fraction comprises the number of cycles during the current program execution phase in which a dispatch stall occurred and the oldest instruction in the load queue was a last-level cache miss divided by total cycles counted in the current program execution phase;
• means for predicting a stall fraction in a next program execution phase based on the measured stall fraction during the current program execution phase and a predicted stall fraction for the current program execution phase;
• and
• means for invoking a dynamic clock and voltage scaling (DCVS) module to apply a frequency setting and a voltage setting during the next program execution phase based on the predicted stall fraction in the next program execution phase.

A method for dynamic clock and voltage scaling, comprising:

• counting, during a current program execution phase, a number of cycles in which a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss;
• measuring a stall fraction during the current program execution phase, wherein measuring the stall fraction comprises dividing the number of cycles during the current program execution phase in which a dispatch stall occurred and the oldest instruction in the load queue was a last-level cache miss by total cycles counted in the current program execution phase;
• predicting a stall fraction in a next program execution phase based on the measured stall fraction during the current program execution phase and a predicted stall fraction for the current program execution phase;
• and
• invoking a dynamic clock and voltage scaling (DCVS) module to apply a frequency setting and a voltage setting during the next program execution phase based on the predicted stall fraction in the next program execution phase.

A non-transitory computer-readable storage medium, wherein the computer-readable storage medium comprises code for causing a processor to:

• count, during a current program execution phase, a number of cycles in which a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss;
• measure a stall fraction during the current program execution phase, wherein measuring the stall fraction comprises dividing the number of cycles during the current program execution phase in which a dispatch stall occurred and the oldest instruction in the load queue was a last-level cache miss by total cycles counted in the current program execution phase;
• predict a stall fraction in a next program execution phase based on the measured stall fraction during the current program execution phase and a predicted stall fraction for the current program execution phase;
• and
• invoke a dynamic clock and voltage scaling (DCVS) module to apply a frequency setting and a voltage setting during the next program execution phase based on the predicted stall fraction in the next program execution phase.