Address and control signal training

An apparatus comprising:

• a memory interface;
• a data processor for generating memory access requests during a normal operation mode and providing said memory access requests to said memory interface using a memory access controller;
• and
• a memory system coupled to said memory interface for receiving and responding to said memory access requests,
• wherein in a training mode, said memory access controller performs command and address training by providing an activation signal and a predetermined address signal with first timing according to a first delay signal, and a plurality of command and address signals except said predetermined address signal with second timing, wherein said second timing is relaxed with respect to said first timing, and said memory access controller determines an eye of timing for said activation signal by repetitively providing a predetermined command on said command and address signals, varying said first delay signal, and measuring a data signal received from said memory interface.

A method for training command and address signals to be provided on a memory interface comprising:

• for each of a plurality of values of a first delay signal:
• issuing a read command to the memory interface by providing an activation signal with first timing based on a clock signal, a selected address signal with said first timing according to said first delay signal, and a plurality of command and additional address signals with second timing, wherein said second timing is relaxed with respect to said first timing;
• and
• receiving a data feedback signal in response to said read command, and
• setting said first delay signal to a selected variable delay corresponding to a data eye of said plurality of values of said first delay signal.