Threshold voltage calibration and compensation circuit for a digital radiographic detector
AssigneeCarestream Health, Inc.
InventorTimothy J. Tredwell
Life of this patent
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Abstract
A two dimensional array of digital imaging pixels each include a photo-sensing element and a readout element. A test element within the two-dimensional array, a column of test elements peripheral to the array, or test monitoring circuits peripheral to the array are constructed using the same process as the readout elements. The test element within the array and the column of test elements are connected to a first and second external voltage sources. The test element within the two-dimensional array and the column of test elements may be connected to a test data line or to a data line used by the imaging pixels.
Claims19
A digital radiographic imaging system comprising:
- a two-dimensional array of imaging pixels in which the imaging pixels each comprise a photo-sensing element and a thin-film-transistor readout element, wherein the readout element comprises a first terminal connected to the photo-sensing element, a second terminal connected to a row select circuit, and a third terminal connected to a readout circuit, and wherein the row select circuit and the readout circuit are disposed outside of the two-dimensional array of imaging pixels;
- a calibration means for measuring changes in voltage thresholds of the thin-film-transistor readout elements wherein the voltage thresholds are modified by one or more of (a) X-ray exposure, (b) environmental exposure, (c) temperature, (d) aging, and (e) aging under electrical stress;
- and
- a compensation circuit for adjusting the voltage thresholds for the thin-film-transistor readout elements based on the measured changes in the threshold voltage of the thin-film-transistors, the compensation circuit comprising:
- a compensation transistor in each of the imaging pixels;
- a column voltage source connected to a first terminal of each of the compensation transistors;
- and
- a row voltage source connected to a second terminal of each of the compensation transistors.
A plurality of digital imaging pixels and test elements arranged in a two-dimensional array of rows and columns, each of the imaging pixels within the array comprising:
- a photo-sensing element electrically connected to a bias voltage source;
- and
- a readout element having a first terminal connected to the photo-sensing element, a second terminal connected to a row select circuit, and a third terminal connected to a readout circuit;
- each of the test elements within the two-dimensional array having a first terminal connected to a first test voltage source, a second terminal connected to a second test voltage source, and a third terminal connected to the readout circuit,
- wherein the bias voltage source, the row select circuit, and the readout circuit are disposed outside of the two-dimensional array of rows and columns, and
- wherein the imaging pixels and the test elements are connected to the readout circuit using data lines, and wherein the readout circuit is configured to measure a level of electrical current on a selected data line as the second test voltage source applies a varying voltage to the second terminal of one of the test elements connected to the selected data line.
A plurality of digital imaging pixels and test elements arranged in a two-dimensional array of rows and columns, each of the imaging pixels within the array comprising:
- a photo-sensing element electrically connected to a bias voltage source;
- and
- a readout element having a first terminal connected to the photo-sensing element, a second terminal connected to a row select circuit, and a third terminal connected to a readout circuit;
- each of the test elements within the two-dimensional array having a first terminal connected to a first test voltage source, a second terminal connected to a second test voltage source, and a third terminal connected to the readout circuit,
- wherein the bias voltage source, the row select circuit, and the readout circuit are disposed outside of the two-dimensional array of rows and columns,
- wherein the further comprises a plurality of test elements disposed outside of the two-dimensional array of rows and columns,
- wherein each of the test elements disposed outside of the two-dimensional array of rows and columns comprise a construction substantially similar to each of the test elements within the two-dimensional array and substantially similar to the readout element of each of the imaging pixels within the array,
- and wherein each of the test elements disposed outside of the two-dimensional array comprises a first terminal, a second terminal, and a third terminal all connected to a corresponding thin film transistor monitoring circuit, the thin film transistor monitoring circuit configured to determine a threshold voltage of the test element connected thereto.
Dependencies are inferred from the claim text.