Stacked memory device and semiconductor memory system including the same

A stacked memory device comprising:

• a base die and a plurality of core dies stacked using a plurality of through-chip electrodes,
• wherein each of the core dies comprises:
• a plurality of input pads capable of receiving column addresses and row addresses externally in a wafer-level test mode;
• an address latch unit capable of latching the row addresses and column addresses received through the input pads to output a row latch address and a column latch address;
• a row signal generation unit capable of decoding the row latch address to generate first row control signals, and generating a first row address based on the row latch address;
• a column signal generation unit capable of decoding the column latch address to generate first column control signals, and generating a first column address based on the column latch address;
• a row signal selection unit capable of selecting one of the first row control signal and a second row control signal received from the base die through a corresponding through-chip electrode based on a wafer-level test enable signal to output a global row control signal, and selecting one of the first row address and a second row address received from the base die through a corresponding through-chip electrode based on the wafer-level test enable signal to output a global row address;
• and
• a column signal selection unit capable of selecting one of the first column control signal and a second column control signal received from the base die through a corresponding through-chip electrode based on the wafer-level test enable signal to output a global column control signal, and selecting one of the first column address and a second column address received from the base die through a corresponding through-chip electrode based on the wafer-level test enable signal to output a global column address.

A stacked memory device comprising:

• a base die and a plurality of core dies stacked using a plurality of through-chip electrodes,
• wherein each of the core dies comprises:
• a plurality of input pads capable of receiving addresses externally in a wafer-level test mode;
• an address latch unit capable of latching the addresses received through the input pads to output latch addresses;
• a decoder capable of decoding the latch addresses to generate a first command pulse signal;
• a first signal selection unit capable of selecting one of the first command pulse signal and a second command pulse signal received from the base die through a corresponding through-chip electrode based on a wafer-level test enable signal to output a source command pulse signal, and selecting one of the latch addresses and addresses received from the base die through corresponding through-chip electrodes based on the wafer-level test enable signal to output a source address;
• and
• a test mode signal generation unit capable of generating a plurality of test mode signals based on the source command pulse signal and the source address.