Backside bulk silicon MEMS
AssigneeIntel Corporation
InventorsRajashree Baskaran, Christopher M. Pelto
Life of this patent
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Abstract
An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.
Claims21
An apparatus comprising:
- a single semiconductor substrate having a frontside and a backside;
- a through-silicon via (TSV) within the semiconductor substrate that extends from the frontside of the substrate to the backside of the substrate;
- and
- a microelectromechanical system (MEMS) device at least partially within the substrate and on the backside of the substrate, wherein the MEMS device comprises a first set of parallel metal plates and a second set of parallel metal plates, each of the first and second sets of parallel metal plates at least partially within the substrate.
An apparatus comprising:
- a single semiconductor substrate;
- a device layer on a frontside of the single semiconductor substrate;
- a redistribution layer on a backside of the single semiconductor substrate;
- a through silicon via (TSV) within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer;
- and
- a microelectromechanical system (MEMS) device at least partially within the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, wherein the MEMS device comprises a first set of parallel metal plates and a second set of parallel metal plates, each of the first and second sets of parallel metal plates at least partially within the substrate.
An apparatus comprising:
- a first substrate having a frontside and a backside;
- a device layer fabricated on the frontside of the first substrate;
- a redistribution layer fabricated on the backside of the first substrate;
- a through-silicon via (TSV) formed through the first substrate, wherein a first end of the TSV is electrically coupled to at least a transistor or at least a metal interconnect of the device layer and a second end of the TSV is electrically coupled to the redistribution layer;
- a first logic-memory interface (LMI) bump fabricated on the backside of the first substrate, wherein the first LMI bump is electrically coupled to the redistribution layer;
- and
- a microelectromechanical system (MEMS) device fabricated on the backside of the first substrate, wherein the MEMS device is electrically coupled to the redistribution layer.
Dependencies are inferred from the claim text.