Stacked complementary FETs featuring vertically stacked horizontal nanowires

A semiconductor structure comprising:

• a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located over a substrate, wherein the plurality of vertically stacked and vertically spaced apart semiconductor nanowires are organized into a lower nanowire array and an upper nanowire array;
• a functional gate structure straddling over the plurality of vertically stacked and vertically spaced apart semiconductor nanowires;
• first epitaxial semiconductor regions of a first conductivity type laterally contacting end walls of the semiconductor nanowires in the lower nanowire array;
• second epitaxial semiconductor regions of a second conductivity type opposite the first conductivity type laterally contacting end walls of the semiconductor nanowires in the upper nanowire array;
• an insulator layer located between the first epitaxial semiconductor region and the second epitaxial semiconductor regions;
• a common source/drain contact structure contacting one of the first epitaxial semiconductor regions and one of the second epitaxial semiconductor regions located on a first side of the functional gate structure;
• and
• a first local source/drain contact structure contacting another of the first epitaxial semiconductor regions located on a second side of the functional gate structure opposite the first side, and a second local source/drain contact structure overlying the first local source/drain contact structure and contacting another of the second epitaxial semiconductor regions located on the second side of the functional gate structure, wherein a trench isolation structure is located between the first local source/drain contact structure and the second local source/drain contact structure.

A semiconductor structure comprising:

• a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located over a substrate, wherein the plurality of vertically stacked and vertically spaced apart semiconductor nanowires are organized into a lower nanowire array and an upper nanowire array;
• a functional gate structure straddling over the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein the functional gate structure comprises a functional gate stack having a first portion located above a topmost semiconductor nanowire of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and a second portion located beneath each semiconductor nanowires of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires;
• first epitaxial semiconductor regions of a first conductivity type laterally contacting end walls of the semiconductor nanowires in the lower nanowire array;
• second epitaxial semiconductor regions of a second conductivity type opposite the first conductivity type laterally contacting end walls of the semiconductor nanowires in the upper nanowire array;
• and
• an insulator layer located between the first epitaxial semiconductor region and the second epitaxial semiconductor regions.